公开(公告)号：US20240162222A1

公开(公告)日：2024-05-16

申请号：US18509870

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L28/20 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813

Abstract: Reliability of a semiconductor device is improved and reduction in yield is reduced. In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. In the semiconductor substrate SUB, a body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. The source region NS, the n-type source region, the n-type drain region, the p-type source region and the p-type drain region are subjected to heat treatment. After heat treatment, a p-type column region PC is formed in the semiconductor substrate SUB located below the body region PB.

公开(公告)号：US20240162143A1

公开(公告)日：2024-05-16

申请号：US18509874

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76885 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a semiconductor substrate SUB, a trench TR is formed.
A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. A body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. An interlayer insulating film IL1 is formed on the upper surface of semiconductor substrate SUB. In the interlayer insulating film IL1, a hole CH1 is formed in the source region NS and in the body region PB. Holes CH3 are formed in the interlayer insulating film IL1 so as to reach the n-type source region, the n-type drain region, the p-type source region and the p-type drain region.