公开(公告)号：US20170287795A1

公开(公告)日：2017-10-05

申请号：US15630725

申请日：2017-06-22

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Tetsuya YOSHIDA ,  Koetsu SAWAI

IPC: H01L21/66 ,  H01L21/265 ,  H01L21/768 ,  G01R31/307 ,  H01L23/535 ,  H01L23/544 ,  H01L27/11 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

公开(公告)号：US20160197021A1

公开(公告)日：2016-07-07

申请号：US15067173

申请日：2016-03-10

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Tetsuya YOSHIDA ,  Koetsu SAWAI

IPC: H01L21/66 ,  H01L23/532 ,  H01L27/11 ,  H01L23/535

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

公开(公告)号：US20150179673A1

公开(公告)日：2015-06-25

申请号：US14470846

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Tetsuya YOSHIDA ,  Koetsu SAWAI

IPC: H01L27/12 ,  H01L23/544 ,  H01L21/66 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

Abstract translation: 当执行用于TEG的VC检查时，通过增加接触插塞的发射强度容易地检测是否发生接触插塞的任何故障，从而提高了半导体器件的可靠性。 SRAM的元件结构形成在芯片区域的SOI衬底上。 此外，在TEG区域中，在从SOI层和BOX膜露出的半导体衬底上形成接触插塞连接到半导体衬底的SRAM的元件结构，作为用于VC检查的TEG。