公开(公告)号：US20230369457A1

公开(公告)日：2023-11-16

申请号：US18186481

申请日：2023-03-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiki YAMAMOTO

IPC: H01L29/66 ,  H01L21/762 ,  H01L27/12 ,  H10B10/00 ,  H01L29/423 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L21/76264 ,  H01L27/1203 ,  H10B10/12 ,  H01L29/42364 ,  H01L21/02293 ,  H01L21/76897

Abstract: A second gate electrode is adjacent, in a Y direction, to a first tip of a semiconductor layer in a first active region such that a protruding distance of a second tip of the second gate electrode protruded, in a X direction, from the semiconductor layer in the first active region is greater than or equal to 0. Also, the first tip of the semiconductor layer in the first active region is covered with a second sidewall spacer. Further, a first epitaxial layer and the second gate electrode are electrically connected to each other via a first shared contact plug formed so as to across the first epitaxial layer, the second sidewall spacer and the second gate electrode.

公开(公告)号：US20220157863A1

公开(公告)日：2022-05-19

申请号：US17514493

申请日：2021-10-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiki YAMAMOTO

IPC: H01L27/13 ,  H01L21/84

Abstract: Improving a reliability of a semiconductor device. A resistive element is comprised of a semiconductor layer of the SOI substrate and an epitaxial semiconductor layer formed on the semiconductor layer. The epitaxial semiconductor layer EP has two semiconductor portions formed on the semiconductor layer and spaced apart from each other. The semiconductor layer has a region on where one of the semiconductor portion is formed, a region on where another of the semiconductor portion is formed, and a region on where the epitaxial semiconductor layer is not formed

公开(公告)号：US20200343268A1

公开(公告)日：2020-10-29

申请号：US16928542

申请日：2020-07-14

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20180138204A1

公开(公告)日：2018-05-17

申请号：US15721901

申请日：2017-09-30

Applicant: Renesas Electronics Corporation

Inventor： Nobuo TSUBOI ,  Yoshiki YAMAMOTO

IPC: H01L27/12 ,  G05F1/625 ,  H01L29/78 ,  H03K17/687

CPC classification number: H01L27/1203 ,  G05F1/625 ,  H01L21/8238 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/02 ,  H01L27/0207 ,  H01L27/1244 ,  H01L29/41733 ,  H01L29/78 ,  H03K17/687

Abstract: Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.

公开(公告)号：US20160197021A1

公开(公告)日：2016-07-07

申请号：US15067173

申请日：2016-03-10

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Tetsuya YOSHIDA ,  Koetsu SAWAI

IPC: H01L21/66 ,  H01L23/532 ,  H01L27/11 ,  H01L23/535

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

公开(公告)号：US20150179673A1

公开(公告)日：2015-06-25

申请号：US14470846

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Tetsuya YOSHIDA ,  Koetsu SAWAI

IPC: H01L27/12 ,  H01L23/544 ,  H01L21/66 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

Abstract translation: 当执行用于TEG的VC检查时，通过增加接触插塞的发射强度容易地检测是否发生接触插塞的任何故障，从而提高了半导体器件的可靠性。 SRAM的元件结构形成在芯片区域的SOI衬底上。 此外，在TEG区域中，在从SOI层和BOX膜露出的半导体衬底上形成接触插塞连接到半导体衬底的SRAM的元件结构，作为用于VC检查的TEG。

公开(公告)号：US20240395823A1

公开(公告)日：2024-11-28

申请号：US18795310

申请日：2024-08-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20230253456A1

公开(公告)日：2023-08-10

申请号：US18135426

申请日：2023-04-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

CPC classification number: H01L29/1083 ,  H01L21/74 ,  H01L21/84 ,  H01L21/265 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20190206744A1

公开(公告)日：2019-07-04

申请号：US16192435

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MARUYAMA ,  Yoshiki YAMAMOTO ,  Toshiya SAITOH

IPC: H01L21/84 ,  H01L21/311 ,  H01L21/265 ,  H01L21/02 ,  H01L27/12

Abstract: A substrate including an insulating layer, a semiconductor layer, and an insulating film stacked on a semiconductor substrate and having a trench filled with an element isolation portion is provided. After removal of the insulating film from a bulk region by a first dry etching, the semiconductor layer is removed from the bulk region by a second dry etching. Then, the insulating film in an SOI region and the insulating layer in the bulk region are removed. A gas containing a fluorocarbon gas is used for first dry etching. The etching thickness of the element isolation portion by a first dry etching is at least equal to the sum of the thicknesses of the insulating film just before starting the first dry etching and the semiconductor layer just before starting the first dry etching. After first dry etching and before second dry etching, oxygen plasma treatment is performed.

公开(公告)号：US20180342537A1

公开(公告)日：2018-11-29

申请号：US15917607

申请日：2018-03-10

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L29/78 ,  H01L29/167 ,  H01L29/423

CPC classification number: H01L27/1207 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/167 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7834

Abstract: An SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer is provided. A first region is one for forming a low breakdown voltage MISFET in the semiconductor layer, and a second region, in which the insulating layer and the semiconductor layer have been removed, is one for forming a high breakdown voltage MISFET. After an n-type semiconductor region is formed in the second region and an n-type extension region is formed in the first region, a first heat treatment is performed on the semiconductor substrate. Thereafter, a diffusion layer is formed in each of the first and second regions, and then a second heat treatment is performed on the semiconductor substrate. Herein, the time for which the first heat treatment is performed is longer than the time for which the second heat treatment is performed.