公开(公告)号：US20140070287A1

公开(公告)日：2014-03-13

申请号：US13965559

申请日：2013-08-13

Applicant: Renesas Electronics Corporation

Inventor： Ming ZHANG ,  Yasuki YOSHIHISA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76237 ,  H01L21/26586 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66477 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: To provide a semiconductor device and a manufacturing method thereof achieving both reduction in ON resistance and increase in breakdown voltage and suppressing a short circuit. The semiconductor device has, in its semiconductor substrate having a main surface, a p− type epitaxial region, n− type epitaxial region, n type offset region, and p type body region configuring a pn junction therewith; and further has a p+ type buried region between the p− type and n− type epitaxial regions, isolation trench extending from the main surface to the p+ type buried region, and trench sidewall n type region formed on at least a portion of the sidewall of the isolation trench. The n type impurity concentration in the trench sidewall n type region is higher than that in the n− type epitaxial region. The trench sidewall n type region extends along the sidewall to reach the p+ type buried region.

Abstract translation: 提供一种半导体器件及其制造方法，其实现了导通电阻的降低和击穿电压的增加以及抑制短路。 半导体器件在其半导体衬底中具有一个p型外延区域，n型外延区域，n型偏移区域以及与其构成pn结的p型体区域; 并且还具有在p型和n型外延区之间的p +型掩埋区，从主表面延伸到p +型掩埋区的隔离沟槽和形成在侧壁的至少一部分上的沟槽侧壁n型区域 隔离沟。 沟槽侧壁n型区域中的n型杂质浓度高于n型外延区域中的n型杂质浓度。 沟槽侧壁n型区域沿着侧壁延伸以到达p +型掩埋区域。

公开(公告)号：US20150303096A1

公开(公告)日：2015-10-22

申请号：US14753212

申请日：2015-06-29

Applicant: Renesas Electronics Corporation

Inventor： Ming ZHANG ,  Yasuki YOSHIHISA

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L21/76237 ,  H01L21/26586 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66477 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: To provide a semiconductor device and a manufacturing method thereof achieving both reduction in ON resistance and increase in breakdown voltage and suppressing a short circuit. The semiconductor device has, in its semiconductor substrate having a main surface, a p− type epitaxial region, n− type epitaxial region, n type offset region, and p type body region configuring a pn junction therewith; and further has a p+ type buried region between the p− type and n− type epitaxial regions, isolation trench extending from the main surface to the p+ type buried region, and trench sidewall n type region formed on at least a portion of the sidewall of the isolation trench. The n type impurity concentration in the trench sidewall n type region is higher than that in the n− type epitaxial region. The trench sidewall n type region extends along the sidewall to reach the p+ type buried region.

Abstract translation: 提供一种半导体器件及其制造方法，其实现了导通电阻的降低和击穿电压的增加以及抑制短路。 半导体器件在其半导体衬底中具有一个p型外延区域，n型外延区域，n型偏移区域以及与其构成pn结的p型体区域; 并且还具有在p型和n型外延区之间的p +型掩埋区，从主表面延伸到p +型掩埋区的隔离沟槽和形成在侧壁的至少一部分上的沟槽侧壁n型区域 隔离沟。 沟槽侧壁n型区域中的n型杂质浓度高于n型外延区域中的n型杂质浓度。 沟槽侧壁n型区域沿着侧壁延伸以到达p +型掩埋区域。