公开(公告)号：US20140070287A1

公开(公告)日：2014-03-13

申请号：US13965559

申请日：2013-08-13

Applicant: Renesas Electronics Corporation

Inventor： Ming ZHANG ,  Yasuki YOSHIHISA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76237 ,  H01L21/26586 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66477 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: To provide a semiconductor device and a manufacturing method thereof achieving both reduction in ON resistance and increase in breakdown voltage and suppressing a short circuit. The semiconductor device has, in its semiconductor substrate having a main surface, a p− type epitaxial region, n− type epitaxial region, n type offset region, and p type body region configuring a pn junction therewith; and further has a p+ type buried region between the p− type and n− type epitaxial regions, isolation trench extending from the main surface to the p+ type buried region, and trench sidewall n type region formed on at least a portion of the sidewall of the isolation trench. The n type impurity concentration in the trench sidewall n type region is higher than that in the n− type epitaxial region. The trench sidewall n type region extends along the sidewall to reach the p+ type buried region.

Abstract translation: 提供一种半导体器件及其制造方法，其实现了导通电阻的降低和击穿电压的增加以及抑制短路。 半导体器件在其半导体衬底中具有一个p型外延区域，n型外延区域，n型偏移区域以及与其构成pn结的p型体区域; 并且还具有在p型和n型外延区之间的p +型掩埋区，从主表面延伸到p +型掩埋区的隔离沟槽和形成在侧壁的至少一部分上的沟槽侧壁n型区域 隔离沟。 沟槽侧壁n型区域中的n型杂质浓度高于n型外延区域中的n型杂质浓度。 沟槽侧壁n型区域沿着侧壁延伸以到达p +型掩埋区域。

公开(公告)号：US20160064559A1

公开(公告)日：2016-03-03

申请号：US14835373

申请日：2015-08-25

Applicant: Renesas Electronics Corporation

Inventor： Mikio TSUJIUCHI ,  Kouji TANAKA ,  Yasuki YOSHIHISA ,  Shunji KUBO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816

Abstract: A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an n+ drain region toward an n+ source region. The plurality of trenches each have a conducting layer therein extending in the main surface in the direction from the n+ drain region toward the n+ source region.

Abstract translation: 半导体衬底具有主表面，其具有n型偏移区域，其具有由沿从n +漏极区域朝向n +源极区域的方向延伸的多个沟槽形成的沟槽部分。 多个沟槽中的导电层各自在从n +漏极区域向n +源极区域的方向上在主表面上延伸。

公开(公告)号：US20160056149A1

公开(公告)日：2016-02-25

申请号：US14809118

申请日：2015-07-24

Applicant: Renesas Electronics Corporation

Inventor： Yasuki YOSHIHISA ,  Ryoji MATSUDA

IPC: H01L27/02 ,  H01L29/06 ,  H01L49/02 ,  H01L29/861

CPC classification number: H01L27/0288 ,  H01L27/0255 ,  H01L29/36 ,  H01L29/8611

Abstract: A P-type epitaxial growth layer is formed on a P-type semiconductor substrate with an N-type buried region and a P-type buried region interposed therebetween. A cathode region, an anode region, and an N-type sinker region are formed in P-type epitaxial growth layer. A resistance element is formed on a surface of an isolation region that electrically isolates anode region and N-type sinker region. Resistance element has: one end portion electrically connected to each of anode region and N-type sinker region; and the other end portion electrically connected to a ground potential.

Abstract translation: 在P型半导体衬底上形成P型外延生长层，其中N型掩埋区和P型埋入区之间插入。 在P型外延生长层中形成阴极区域，阳极区域和N型沉降弧区域。 在隔离区域的电绝缘阳极区域和N型沉降片区域的表面上形成电阻元件。 电阻元件具有：电连接到阳极区域和N型沉降片区域中的每一个的一个端部; 并且另一端部电连接到地电位。

公开(公告)号：US20150303096A1

公开(公告)日：2015-10-22

申请号：US14753212

申请日：2015-06-29

Applicant: Renesas Electronics Corporation

Inventor： Ming ZHANG ,  Yasuki YOSHIHISA

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L21/76237 ,  H01L21/26586 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66477 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: To provide a semiconductor device and a manufacturing method thereof achieving both reduction in ON resistance and increase in breakdown voltage and suppressing a short circuit. The semiconductor device has, in its semiconductor substrate having a main surface, a p− type epitaxial region, n− type epitaxial region, n type offset region, and p type body region configuring a pn junction therewith; and further has a p+ type buried region between the p− type and n− type epitaxial regions, isolation trench extending from the main surface to the p+ type buried region, and trench sidewall n type region formed on at least a portion of the sidewall of the isolation trench. The n type impurity concentration in the trench sidewall n type region is higher than that in the n− type epitaxial region. The trench sidewall n type region extends along the sidewall to reach the p+ type buried region.

Abstract translation: 提供一种半导体器件及其制造方法，其实现了导通电阻的降低和击穿电压的增加以及抑制短路。 半导体器件在其半导体衬底中具有一个p型外延区域，n型外延区域，n型偏移区域以及与其构成pn结的p型体区域; 并且还具有在p型和n型外延区之间的p +型掩埋区，从主表面延伸到p +型掩埋区的隔离沟槽和形成在侧壁的至少一部分上的沟槽侧壁n型区域 隔离沟。 沟槽侧壁n型区域中的n型杂质浓度高于n型外延区域中的n型杂质浓度。 沟槽侧壁n型区域沿着侧壁延伸以到达p +型掩埋区域。