公开(公告)号：US20140147982A1

公开(公告)日：2014-05-29

申请号：US14091247

申请日：2013-11-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tamotsu OGATA ,  Toshifumi IWASAKI

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided is a semiconductor device with improved performance and production yield. Insulating films IL2 and IL3 are formed over a semiconductor substrate in that order to cover a gate electrode. Then, the insulating films IL3 and IL2 are etched back to form sidewall spacers including the insulating films IL2 and IL3 over sidewalls of the gate electrode. The source/drain region is formed in the semiconductor substrate by ion implantation using the gate electrode and the sidewall spacer as a mask. Then, the sidewall spacers are isotropically etched on conditions where the insulating film IL2 is less likely to be etched than the third insulating film IL3 to thereby decrease the thickness of the sidewall spacer. Thereafter, a reaction layer between the metal and the source/drain region is formed over the source/drain region.

Abstract translation: 提供了具有改进的性能和产量的半导体器件。 绝缘膜IL2和IL3以这种顺序形成在半导体衬底上以覆盖栅电极。 然后，绝缘膜IL3和IL2被回蚀以在栅电极的侧壁上形成包括绝缘膜IL2和IL3的侧壁间隔物。 源极/漏极区域通过使用栅电极和侧壁间隔物作为掩模的离子注入形成在半导体衬底中。 然后，在绝缘膜IL2比第三绝缘膜IL3不太可能被蚀刻的条件下，侧壁间隔物被各向同性蚀刻，从而减小侧壁间隔物的厚度。 此后，在源极/漏极区域上形成金属和源极/漏极区域之间的反应层。

公开(公告)号：US20170287970A1

公开(公告)日：2017-10-05

申请号：US15630693

申请日：2017-06-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshifumi IWASAKI

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14614 ,  H01L27/1462 ,  H01L27/14689

Abstract: Provided is a semiconductor device with improved performance. In a method for manufacturing a semiconductor device, after forming a gate electrode of a transfer transistor over a p-type well, a photodiode is formed in one part of the p-type well positioned on one side with respect to the gate electrode. Then, a cap insulating film including silicon and nitrogen is formed over the photodiode before implanting impurity ions for formation of an n-type low-concentration semiconductor region of the transfer transistor, into the other part of the p-type well positioned on a side opposite to the one side with respect to the gate electrode.

公开(公告)号：US20160163758A1

公开(公告)日：2016-06-09

申请号：US14949422

申请日：2015-11-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshifumi IWASAKI

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14614 ,  H01L27/1462 ,  H01L27/14689

Abstract: Provided is a semiconductor device with improved performance. In a method for manufacturing a semiconductor device, after forming a gate electrode of a transfer transistor over a p-type well, a photodiode is formed in one part of the p-type well positioned on one side with respect to the gate electrode. Then, a cap insulating film including silicon and nitrogen is formed over the photodiode before implanting impurity ions for formation of an n-type low-concentration semiconductor region of the transfer transistor, into the other part of the p-type well positioned on a side opposite to the one side with respect to the gate electrode.

Abstract translation: 提供了具有改进的性能的半导体器件。 在制造半导体器件的方法中，在p型阱上形成转移晶体管的栅电极之后，在位于相对于栅电极的一侧的p型阱的一部分中形成光电二极管。 然后，在将用于形成转移晶体管的n型低浓度半导体区域的杂质离子注入到位于侧面的p型阱的另一部分中之前，在光电二极管上形成包括硅和氮的帽绝缘膜 相对于栅极电极的一侧相对。

公开(公告)号：US20160276270A1

公开(公告)日：2016-09-22

申请号：US15016360

申请日：2016-02-05

Applicant: Renesas Electronics Corporation

Inventor： Toshifumi IWASAKI ,  Yukio MAKI

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11 ,  H01L23/535

CPC classification number: H01L23/5256 ,  H01L21/76801 ,  H01L21/76831 ,  H01L27/11

Abstract: An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a SRAM memory cell. The bit lines are covered by an interlayer insulating film. As the interlayer insulating film, a boron-doped BPTEOS film is formed. The bit lines have thereabove a fuse. The fuse and the bit lines are electrically coupled to each other via contact plugs. The interlayer insulating film that covers the bit lines therewith is separated from the contact plugs.

Abstract translation: 本发明的目的是提供一种具有较少破裂或剥离的半导体器件及其制造方法。 半导体器件的熔丝部分具有电耦合到SRAM存储单元的位线。 位线被层间绝缘膜覆盖。 作为层间绝缘膜，形成硼掺杂BPTEOS膜。 位线上面有一个保险丝。 保险丝和位线通过接触插头彼此电耦合。 覆盖其位线的层间绝缘膜与接触插塞分离。