公开(公告)号：US20150234661A1

公开(公告)日：2015-08-20

申请号：US14704589

申请日：2015-05-05

Applicant: Renesas Electronics Corporation

Inventor： Hiromichi YAMADA ,  Nobuyasu KANEKAWA ,  Tsutomu YAMADA ,  Kesami HAGIWARA

IPC: G06F9/30 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/30145 ,  G06F9/4881 ,  G06F11/1492 ,  G06F11/1497 ,  G06F11/1641 ,  G06F11/1691 ,  G06F11/2041 ,  G06F11/3024 ,  G06F11/3404 ,  G06F21/566

Abstract: A processor system, includes a first central processing unit (CPU) that executes a redundant instruction set; and a second CPU that executes the redundant instruction set, wherein before the second CPU executes a redundant instruction among the redundant instruction set, the first CPU is able to execute n (n is a predetermined integer number) redundant instructions among the redundant instruction set, and wherein when an exception occurs during execution of the redundant instruction set in the first CPU, the first CPU executes an instruction for the exception as a non-redundant instruction.

Abstract translation: 处理器系统包括执行冗余指令集的第一中央处理单元（CPU） 以及执行所述冗余指令集的第二CPU，其中在所述第二CPU在所述冗余指令集中执行冗余指令之前，所述第一CPU能够执行所述冗余指令集中的n（n为预定整数）冗余指令， 并且其中当在执行所述第一CPU中的所述冗余指令集时发生异常时，所述第一CPU执行所述异常指令作为非冗余指令。