公开(公告)号：US20190020849A1

公开(公告)日：2019-01-17

申请号：US16133351

申请日：2018-09-17

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki HAMASAKI ,  Atsushi NAKAMURA ,  Manabu KOIKE ,  Hideaki KIDO ,  Nobuyasu KANEKAWA

IPC: H04N5/77 ,  H04N5/232 ,  G06T1/20 ,  H04N5/91 ,  H04N5/265 ,  G06T1/60

CPC classification number: H04N5/77 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28 ,  H04N5/23229 ,  H04N5/265 ,  H04N5/91

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

公开(公告)号：US20180241964A1

公开(公告)日：2018-08-23

申请号：US15961985

申请日：2018-04-25

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki HAMASAKI ,  Atsushi NAKAMURA ,  Manabu KOIKE ,  Hideaki KIDO ,  Nobuyasu KANEKAWA

IPC: H04N5/77 ,  H04N5/232 ,  G06T1/20 ,  H04N5/91 ,  H04N5/265 ,  G06T1/60

CPC classification number: H04N5/77 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28 ,  H04N5/23229 ,  H04N5/265 ,  H04N5/91

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

公开(公告)号：US20170034471A1

公开(公告)日：2017-02-02

申请号：US15290831

申请日：2016-10-11

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki HAMASAKI ,  Atsushi NAKAMURA ,  Manabu KOIKE ,  Hideaki KIDO ,  Nobuyasu KANEKAWA

IPC: H04N5/77 ,  G06T1/20 ,  H04N5/265 ,  H04N5/91 ,  H04N5/232 ,  G06T1/60

CPC classification number: H04N5/77 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28 ,  H04N5/23229 ,  H04N5/265 ,  H04N5/91

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract translation: 图像处理装置包括图像处理单元，其从一个图像数据计算两种图像数据并输出计算出的图像数据;数据组合单元，其组合从图像处理单元提供的两种数据，并将该组合数据输出到 一个终端，输出缓冲器，根据从用于仲裁总线的总线仲裁装置提供的指令调整组合数据的输出定时;以及数据分配单元，其以从形式输出从输出缓冲器输出到总线的组合数据 或者分发组合数据，并根据外部组合分配指令将分布式数据输出到总线。

公开(公告)号：US20150234661A1

公开(公告)日：2015-08-20

申请号：US14704589

申请日：2015-05-05

Applicant: Renesas Electronics Corporation

Inventor： Hiromichi YAMADA ,  Nobuyasu KANEKAWA ,  Tsutomu YAMADA ,  Kesami HAGIWARA

IPC: G06F9/30 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/30145 ,  G06F9/4881 ,  G06F11/1492 ,  G06F11/1497 ,  G06F11/1641 ,  G06F11/1691 ,  G06F11/2041 ,  G06F11/3024 ,  G06F11/3404 ,  G06F21/566

Abstract: A processor system, includes a first central processing unit (CPU) that executes a redundant instruction set; and a second CPU that executes the redundant instruction set, wherein before the second CPU executes a redundant instruction among the redundant instruction set, the first CPU is able to execute n (n is a predetermined integer number) redundant instructions among the redundant instruction set, and wherein when an exception occurs during execution of the redundant instruction set in the first CPU, the first CPU executes an instruction for the exception as a non-redundant instruction.

Abstract translation: 处理器系统包括执行冗余指令集的第一中央处理单元（CPU） 以及执行所述冗余指令集的第二CPU，其中在所述第二CPU在所述冗余指令集中执行冗余指令之前，所述第一CPU能够执行所述冗余指令集中的n（n为预定整数）冗余指令， 并且其中当在执行所述第一CPU中的所述冗余指令集时发生异常时，所述第一CPU执行所述异常指令作为非冗余指令。

公开(公告)号：US20150339201A1

公开(公告)日：2015-11-26

申请号：US14705127

申请日：2015-05-06

Applicant: Renesas Electronics Corporation

Inventor： Nobuyasu KANEKAWA ,  Hitoshi ARIMITSU ,  Takashi YASUMASU ,  Hideki MATSUYAMA

IPC: G06F11/20

CPC classification number: G06F11/2053 ,  G06F11/1616 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/183 ,  G06F11/187 ,  G06F2201/85

Abstract: The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

Abstract translation: 本发明提供一种微控制器，即使在故障时也可以继续操作，而不使存储器冗余以抑制芯片面积的增加。 微控制器包括并行执行相同处理的三个或更多个处理器和存储设备。 存储装置包括具有不冗余的存储区域，地址选择部分，数据输出部分和故障恢复部分的存储器垫。 地址选择部分基于处理器访问时发出的三个或更多个地址来选择存储器存储器中的存储区域。 数据输出部分从由地址选择部分选择的存储器堆中的存储区域读取数据。 故障恢复部件校正或掩蔽发生在存储器垫，地址选择部分和数据输出部分中的预定数量或更少的故障。