公开(公告)号：US20180350430A1

公开(公告)日：2018-12-06

申请号：US16059255

申请日：2018-08-09

Applicant: Renesas Electronics Corporation

Inventor： Shigenobu KOMATSU ,  Masanao YAMAOKA ,  Noriaki MAEDA ,  Masao MORIMOTO ,  Yasuhisa SHIMAZAKI ,  Yasuyuki OKUMA ,  Toshiaki SANO

IPC: G11C11/417 ,  H01L27/11 ,  G11C5/06 ,  G11C11/413 ,  G11C5/14 ,  H01L27/092

CPC classification number: G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

公开(公告)号：US20160172022A1

公开(公告)日：2016-06-16

申请号：US15050074

申请日：2016-02-22

Applicant: Renesas Electronics Corporation

Inventor： Shigenobu KOMATSU ,  Masanao YAMAOKA ,  Noriaki MAEDA ,  Masao MORIMOTO ,  Yasuhisa SHIMAZAKI ,  Yasuyuki OKUMA ,  Toshiaki SANO

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract translation: 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

公开(公告)号：US20170309327A1

公开(公告)日：2017-10-26

申请号：US15648702

申请日：2017-07-13

Applicant: Renesas Electronics Corporation

Inventor： Shigenobu KOMATSU ,  Masanao YAMAOKA ,  Noriaki MAEDA ,  Masao MORIMOTO ,  Yasuhisa SHIMAZAKI ,  Yasuyuki OKUMA ,  Toshiaki SANO

IPC: G11C11/417 ,  G11C11/413 ,  G11C5/06 ,  G11C5/14 ,  H01L27/11 ,  H01L27/092

CPC classification number: G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.