公开(公告)号：US20180350430A1

公开(公告)日：2018-12-06

申请号：US16059255

申请日：2018-08-09

Applicant: Renesas Electronics Corporation

Inventor： Shigenobu KOMATSU ,  Masanao YAMAOKA ,  Noriaki MAEDA ,  Masao MORIMOTO ,  Yasuhisa SHIMAZAKI ,  Yasuyuki OKUMA ,  Toshiaki SANO

IPC: G11C11/417 ,  H01L27/11 ,  G11C5/06 ,  G11C11/413 ,  G11C5/14 ,  H01L27/092

CPC classification number: G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

公开(公告)号：US20180240513A1

公开(公告)日：2018-08-23

申请号：US15957263

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US20190006375A1

公开(公告)日：2019-01-03

申请号：US16123396

申请日：2018-09-06

Applicant: Renesas Electronics Corporation

Inventor： Masao MORIMOTO ,  Noriaki MAEDA ,  Yasuhisa SHIMAZAKI

IPC: H01L27/11 ,  H01L27/092 ,  H01L23/528 ,  H01L27/02 ,  G11C11/412 ,  G06F17/50

CPC classification number: H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

公开(公告)号：US20170092352A1

公开(公告)日：2017-03-30

申请号：US15373783

申请日：2016-12-09

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US20130272058A1

公开(公告)日：2013-10-17

申请号：US13874834

申请日：2013-05-01

Applicant: Renesas Electronics Corporation

Inventor： Noriaki MAEDA ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US20160276352A1

公开(公告)日：2016-09-22

申请号：US15165651

申请日：2016-05-26

Applicant: Renesas Electronics Corporation

Inventor： Masao MORIMOTO ,  Noriaki MAEDA ,  Yasuhisa SHIMAZAKI

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

Abstract translation: 一种具有SRAM的半导体器件，包括：第一晶体管和第五晶体管设置在其中的单片第一有源区; 与第一有源区分离的第二有源区，其中设置第二晶体管; 其中设置第三晶体管和第六晶体管的单片第三有源区; 以及与第三有源区分离的第四有源区，其中设置第四晶体管。 每个驱动晶体管分为第一晶体管和第二晶体管（或第三晶体管和第四晶体管），并且这些驱动晶体管设置在不同的有源区域上。

公开(公告)号：US20160240246A1

公开(公告)日：2016-08-18

申请号：US15134981

申请日：2016-04-21

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US20160172022A1

公开(公告)日：2016-06-16

申请号：US15050074

申请日：2016-02-22

Applicant: Renesas Electronics Corporation

Inventor： Shigenobu KOMATSU ,  Masanao YAMAOKA ,  Noriaki MAEDA ,  Masao MORIMOTO ,  Yasuhisa SHIMAZAKI ,  Yasuyuki OKUMA ,  Toshiaki SANO

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract translation: 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

公开(公告)号：US20150380076A1

公开(公告)日：2015-12-31

申请号：US14835127

申请日：2015-08-25

Applicant: Renesas Electronics Corporation

Inventor： Noriaki MAEDA ,  Yoshihiro SHINOZAKI ,  Masanao YAMAOKA ,  Yasuhisa SHIMAZAKI ,  Masanori ISODA ,  Koji NII

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

Abstract translation: 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US20170309327A1

公开(公告)日：2017-10-26

申请号：US15648702

申请日：2017-07-13

Applicant: Renesas Electronics Corporation

Inventor： Shigenobu KOMATSU ,  Masanao YAMAOKA ,  Noriaki MAEDA ,  Masao MORIMOTO ,  Yasuhisa SHIMAZAKI ,  Yasuyuki OKUMA ,  Toshiaki SANO

IPC: G11C11/417 ,  G11C11/413 ,  G11C5/06 ,  G11C5/14 ,  H01L27/11 ,  H01L27/092

CPC classification number: G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.