公开(公告)号：US08261006B2

公开(公告)日：2012-09-04

申请号：US11960601

申请日：2007-12-19

申请人： Richard Chen ,  Ping Hou ,  Chih Hsueh

发明人： Richard Chen ,  Ping Hou ,  Chih Hsueh

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/214 ,  G06F2212/7203

摘要： Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.

摘要翻译： 本文描述了用于提高闪存固态驱动装置的性能和可靠性的系统和方法。 闪存阵列组件存储数据。 存储器层次组件在主机和闪存阵列组件之间传输数据。 存储器层级组件包括耦合到合并缓冲器的一级（“L1”）高速缓存，闪存阵列组件和主机。 合并缓冲器耦合到闪存阵列组件。 L1缓存和合并缓冲区包括易失性存储器，并且主机耦合到合并缓冲区和闪存阵列组件。 存储器层级组件包括写入组件和读取组件。 写入组件将数据写入L1高速缓存，合并缓冲区或闪存阵列组件中的至少一个。 读取组件从L1高速缓存，合并缓冲器或闪存阵列组件中的至少一个读取数据。

公开(公告)号：US20090164700A1

公开(公告)日：2009-06-25

申请号：US11960601

申请日：2007-12-19

申请人： Richard Chen ,  Ping Hou ,  Chih Hsueh

发明人： Richard Chen ,  Ping Hou ,  Chih Hsueh

IPC分类号： G06F12/02

CPC分类号： G06F12/0866 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/214 ,  G06F2212/7203

摘要： Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.

摘要翻译： 本文描述了用于提高闪存固态驱动装置的性能和可靠性的系统和方法。 闪存阵列组件存储数据。 存储器层次组件在主机和闪存阵列组件之间传输数据。 存储器层级组件包括耦合到合并缓冲器的一级（“L1”）高速缓存，闪存阵列组件和主机。 合并缓冲器耦合到闪存阵列组件。 L1缓存和合并缓冲区包括易失性存储器，并且主机耦合到合并缓冲区和闪存阵列组件。 存储器层级组件包括写入组件和读取组件。 写入组件将数据写入L1高速缓存，合并缓冲区或闪存阵列组件中的至少一个。 读取组件从L1高速缓存，合并缓冲器或闪存阵列组件中的至少一个读取数据。

公开(公告)号：US07761740B2

公开(公告)日：2010-07-20

申请号：US11955934

申请日：2007-12-13

申请人： Wiliam Kern ,  Chih Hsueh ,  Ping Hou

发明人： Wiliam Kern ,  Chih Hsueh ,  Ping Hou

IPC分类号： G06F11/00

CPC分类号： G06F12/0246 ,  G06F11/1064 ,  G06F11/1441 ,  G06F2212/7201 ,  G06F2212/7203

摘要： Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error.

摘要翻译： 提供将系统地址与物理地址分离的存储器系统中的地址转换的准确性的系统和/或方法。 地址修改事务被记录在非易失性写入缓冲器中以将时间转换的物理地址/位置与当前翻译的物理位置/地址耦合。 此外，完整性检查保护可以应用于转换和写入数据，以限制在写入操作期间发生故障/错误的情况下可能丢失的数据量。 事务记录和完整性检查保护允许恢复由于故障/错误而可能未完全完成的写入操作。

公开(公告)号：US20090158085A1

公开(公告)日：2009-06-18

申请号：US11955934

申请日：2007-12-13

申请人： William Kern ,  Chih Hsueh ,  Ping Hou

发明人： William Kern ,  Chih Hsueh ,  Ping Hou

IPC分类号： G06F12/16 ,  G06F12/10 ,  G06F11/10

CPC分类号： G06F12/0246 ,  G06F11/1064 ,  G06F11/1441 ,  G06F2212/7201 ,  G06F2212/7203

摘要： Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error.

摘要翻译： 提供将系统地址与物理地址分离的存储器系统中的地址转换的准确性的系统和/或方法。 地址修改事务被记录在非易失性写入缓冲器中以将时间转换的物理地址/位置与当前翻译的物理位置/地址耦合。 此外，完整性检查保护可以应用于转换和写入数据，以限制在写入操作期间发生故障/错误的情况下可能丢失的数据量。 事务记录和完整性检查保护允许恢复由于故障/错误而可能未完全完成的写入操作。

公开(公告)号：US20050198092A1

公开(公告)日：2005-09-08

申请号：US10790205

申请日：2004-03-02

申请人： Jia-Pei Shen ,  Chien-Meen Hwang ,  Chih Hsueh ,  Orlando Canelones

发明人： Jia-Pei Shen ,  Chien-Meen Hwang ,  Chih Hsueh ,  Orlando Canelones

IPC分类号： G06F17/14 ,  G06F15/00

CPC分类号： G06F17/142

摘要： An FFT circuit is implemented using a radix-4 butterfly element and a partitioned memory for storage of a prescribed number of data values. The radix-4 butterfly element is configured for performing an FFT operation in a prescribed number of stages, each stage including a prescribed number of in-place computation operations relative to the prescribed number of data values. The partitioned memory includes a first memory portion and a second memory portion, and the data values for the FFT circuit are divided equally for storage in the first and second memory portions in a manner that ensures that each in-place computation operation is based on retrieval of an equal number of data values retrieved from each of the first and second memory portions.

摘要翻译： 使用基数-4蝶形元件和分区存储器来实现FFT电路，用于存储规定数量的数据值。 基数-4蝶形元件被配置为执行规定数量级的FFT运算，每个级包括相对于规定数量的数据值的规定数量的就地计算操作。 分区存储器包括第一存储器部分和第二存储器部分，并且以确保每个就地计算操作基于检索的方式将用于FFT电路的数据值均等地分配以存储在第一和第二存储器部分中 从第一和第二存储器部分中的每一个检索的相等数量的数据值。

公开(公告)号：US20050122895A1

公开(公告)日：2005-06-09

申请号：US10727670

申请日：2003-12-05

申请人： Xu Zhou ,  Chihming Chen ,  Chih Hsueh ,  Orlando Canelones

发明人： Xu Zhou ,  Chihming Chen ,  Chih Hsueh ,  Orlando Canelones

IPC分类号： H04L27/26 ,  H04J11/00

CPC分类号： H04L27/2657 ,  H04L27/266

摘要： An OFDM receiver configured for measuring frequency error based on comparing prescribed pilot tones from a prescribed group of consecutive symbols in a received OFDM signal. A complex conjugate generator is configured for generating complex conjugates of the prescribed pilot tones of a first subgroup of the consecutive symbols. A multiplier is configured for generating a complex pilot product, for each symbol subgroup position, by multiplying the pilot tones of a second subgroup symbol at the corresponding symbol subgroup position with the respective complex conjugates of the first subgroup symbol at the corresponding symbol subgroup position. A complex summation circuit sums the complex pilot products of the symbol subgroup positions to obtain an accumulated complex value. A error calculator calculates the frequency error from the accumulated complex value for use in correcting frequency offset.

摘要翻译： OFDM接收器，被配置为基于在接收的OFDM信号中比较来自规定的连续符号组的规定导频音来测量频率误差。 复共轭发生器被配置用于产生连续符号的第一子组的规定导频音调的复共轭。 乘法器被配置为通过将相应符号子组位置处的第二子组符号的导频音调与相应符号子组位置处的第一子组符号的相应复共轭相乘来为每个符号子组位置生成复合导频乘积。 复数求和电路将符号子组位置的复合导频乘积相加以获得累积的复数值。 误差计算器根据用于校正频率偏移的累加复数值计算频率误差。