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    Interface for writing to memories having different write times
    1.
    发明授权
    Interface for writing to memories having different write times 失效
    用于写入具有不同写入时间的存储器的接口

    公开(公告)号：US07698511B2

    公开(公告)日：2010-04-13

    申请号：US11132860

    申请日：2005-05-19

    申请人： Richard F. Hess ,  Kent A. Stange

    发明人： Richard F. Hess ,  Kent A. Stange

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F11/00 ,  G11C7/10

    CPC分类号： G11C29/02 ,  G06F11/141 ,  G06F13/1694 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012

    摘要： An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.

    摘要翻译： 描述具有不同写入时间的存储器之间的接口。 接口包括用于在由第一存储器设备的处理器进行的存储器访问期间捕获地址和数据信息的锁存器。 接口还包括用于提供帧管理的索引计数器。 接口还包括用于确定要写入第二存储器设备中的数据和地址生成逻辑的可变标识阵列逻辑，以确定数据将被存储在第二存储器设备中的位置。 此外，该接口包括数据有效性逻辑，以确保写入第二存储器件的数据有效。 结果，处理器可以基本上实时地操作，并且可以使用存储在第二存储器设备中的数据检测事件不正常之后恢复自身。

    INTERFACE FOR WRITING TO MEMORIES HAVING DIFFERENT WRITE TIMES
    2.
    发明申请
    INTERFACE FOR WRITING TO MEMORIES HAVING DIFFERENT WRITE TIMES 失效
    用于写入具有不同写入时间的记忆的界面

    公开(公告)号：US20100064092A1

    公开(公告)日：2010-03-11

    申请号：US11132860

    申请日：2005-05-19

    申请人： Richard F. Hess ,  Kent A. Stange

    发明人： Richard F. Hess ,  Kent A. Stange

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G11C29/02 ,  G06F11/141 ,  G06F13/1694 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012

    摘要： An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.

    摘要翻译： 描述具有不同写入时间的存储器之间的接口。 接口包括用于在由第一存储器设备的处理器进行的存储器访问期间捕获地址和数据信息的锁存器。 接口还包括用于提供帧管理的索引计数器。 接口还包括用于确定要写入第二存储器设备中的数据和地址生成逻辑的可变标识阵列逻辑，以确定数据将被存储在第二存储器设备中的位置。 此外，该接口包括数据有效性逻辑，以确保写入第二存储器件的数据有效。 结果，处理器可以基本上实时地操作，并且可以使用存储在第二存储器设备中的数据检测事件不正常之后恢复自身。

    High integrity digital processor architecture
    3.
    发明授权
    High integrity digital processor architecture 失效
    高完整性数字处理器架构

    公开(公告)号：US4751670A

    公开(公告)日：1988-06-14

    申请号：US846312

    申请日：1986-03-31

    申请人： Richard F. Hess

    发明人： Richard F. Hess

    IPC分类号： G06F11/14 ,  G06F15/50 ,  G06F11/00 ,  G06F12/00

    CPC分类号： G06F11/1441

    摘要： A digital data processor architecture immune from digital computer upset including a non-volatile random access memory for storing past and present values of state variables. An index counter is utilized to offset the store and retrieve instruction base addresses to effect the multiple storage of the state variables in the non-volatile memory. A monitor detects disruptions in data processing and vectors the processor to a reinitialization and restart routine in which the past values of the state variables are utilized.

    摘要翻译： 数字数据处理器架构免受数字计算机扰乱，包括用于存储状态变量的过去和现在值的非易失性随机存取存储器。 使用索引计数器来偏移存储并检索指令库地址以实现非易失性存储器中状态变量的多次存储。 监视器检测数据处理中的中断，并将处理器转发到重新初始化和重新启动例程，其中使用状态变量的过去值。

    Memory with high integrity memory cells
    5.
    发明授权
    Memory with high integrity memory cells 失效
    具有高完整性内存单元的内存

    公开(公告)号：US6163480A

    公开(公告)日：2000-12-19

    申请号：US998797

    申请日：1997-12-29

    申请人： Richard F. Hess ,  Clarence Scott Smith

    发明人： Richard F. Hess ,  Clarence Scott Smith

    IPC分类号： G11C5/00 ,  G11C11/34

    CPC分类号： G11C5/005

    摘要： A memory system for a digital computer includes a non-volatile random access memory for storing past and present values of state variables is immune from electromagnetic transients and other disturbances which can affect the integrity of the memory. Each memory cell is designed with an energy storage device and logic devices which control the logic sequence for charging of the energy storing devices. These memory cells are aligned in an array and specially designed system is included with this that takes into account the length of time required in order to charge each cell in the array.

    摘要翻译： 用于数字计算机的存储器系统包括用于存储状态变量的过去和现在值的非易失性随机存取存储器免于可能影响存储器的完整性的电磁瞬变和其它干扰。 每个存储单元设计有能量存储装置和控制用于对能量存储装置充电的逻辑顺序的逻辑装置。 这些存储器单元在阵列中对齐，并且特别设计的系统被包括在内，其考虑了为阵列中的每个单元充电所需的时间长度。

    Fault recoverable computer system
    7.
    发明授权
    Fault recoverable computer system 失效
    故障恢复计算机系统

    公开(公告)号：US5313625A

    公开(公告)日：1994-05-17

    申请号：US738011

    申请日：1991-07-30

    申请人： Richard F. Hess ,  Larry J. Yount

    发明人： Richard F. Hess ,  Larry J. Yount

    IPC分类号： G06F11/14 ,  G06F11/16 ,  G06F11/34 ,  G06F11/00

    CPC分类号： G06F11/1633 ,  G06F11/1407 ,  G06F11/1402 ,  G06F11/3466

    摘要： In a computer system having fault recoverable capability, there is included a first and second data processing unit (DPU), wherein each of the first and second DPU is executing the same task essentially in parallel. Each DPU comprises a processor, a memory and a protected memory. The protected memory stores system data, such that the system data stored in the protected memory is immune from transient conditions. Also included is a monitor, which is operatively connected to the monitor of the other DPU. The monitor detects the occurrence of an upset to reinitialize the DPU, the DPU being reinitialized to a condition just prior to the occurrence of the upset thus avoiding utilization of any potentially erroneous data, and thereby permitting the DPU to return to its normal processing with valid data.

    摘要翻译： 在具有故障恢复能力的计算机系统中，包括第一和第二数据处理单元（DPU），其中第一和第二DPU中的每一个基本上并行地执行相同的任务。 每个DPU包括处理器，存储器和受保护的存储器。 受保护的存储器存储系统数据，使得存储在受保护存储器中的系统数据免受瞬态条件的影响。 还包括监视器，其可操作地连接到另一个DPU的监视器。 监视器检测到发生不适，重新初始化DPU，DPU被重新初始化为在发生之前的状况，从而避免利用任何潜在的错误数据，从而允许DPU返回其正常处理，具有有效的 数据。

    Fault recovery mechanism, transparent to digital system function
    8.
    发明授权
    Fault recovery mechanism, transparent to digital system function 失效
    故障恢复机制，对数字系统功能透明

    公开(公告)号：US4996687A

    公开(公告)日：1991-02-26

    申请号：US256060

    申请日：1988-10-11

    申请人： Richard F. Hess ,  Kurt A. Liebel ,  Larry J. Yount

    发明人： Richard F. Hess ,  Kurt A. Liebel ,  Larry J. Yount

    IPC分类号： G06F12/16 ,  G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20

    CPC分类号： G06F11/141 ,  G06F11/00

    摘要： A method and apparatus allows fault recovery in a digital computer based control system whereby system upsets induced by external transient noise conditions can be accommodated. A CPU is coupled to its main memory and its I/O interfaces by a common address/data bus, these three elements being susceptible to having data thereon or therein corrupted by transient noise. Also coupled to the bus, but in a hardened environment, are first and second supplemental memories which, under memory control, operate on alternating even and odd computational frames defined by the CPU's real-time clock to store the same words as are then being entered into the CPU's main memory. As computational frames are entered into one or the other of these two memories by eaves-dropping on the common bus, the other supplemental memory is transferring its contents to a backup memory which is also housed in the noise-immune environment. The backup memory is connected in a read-only mode to the address/data bus and, because of the manner of operation, always contains the computational frame that is delayed one cycle of the CPU's real-time clock from the frame in progress. Should a transient upset occur, it may be followed by a transfer of the information from the backup memory into the computer's main memory such that computations can then continue with data that is uncorrupted.