公开(公告)号：US20240171074A1

公开(公告)日：2024-05-23

申请号：US18493826

申请日：2023-10-25

Applicant: Richtek Technology Corporation

Inventor： Jiing-Horng Wang ,  Yu-Pin Tseng ,  Chia-Jung Chang ,  Tsan-He Wang ,  Shao-Ming Chang

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M3/33507

Abstract: A switching regulator includes: a power stage circuit, a control circuit and an operation clock signal generator circuit. The operation clock signal generator circuit includes: a time point option unit generating a time point option signal according to a phase node voltage during a ringing period subsequent to a blanking period, to indicate at least one available turn-on time point, or generating a lowest voltage time point signal according to the phase node voltage during a tolerance period, to indicate a lowest voltage time point; and a time point deciding unit deciding the tolerance period according to a base clock signal and a tolerable frequency range and select the available turn-on time point or the lowest voltage time point within the tolerance period as a decided time point, to generate the operation clock signal.

公开(公告)号：US20240128868A1

公开(公告)日：2024-04-18

申请号：US18471331

申请日：2023-09-21

Applicant: Richtek Technology Corporation

Inventor： Chia-Jung Chang ,  Shao-Ming Chang ,  Tsan-He Wang ,  Jiing-Horng Wang ,  Yu-Pin Tseng

IPC: H02M3/157 ,  H02M3/158

CPC classification number: H02M3/157 ,  H02M3/158

Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.