公开(公告)号：US20240014154A1

公开(公告)日：2024-01-11

申请号：US18186974

申请日：2023-03-21

Applicant: Richtek Technology Corporation

Inventor： Wu-Te WENG ,  Yong-Zhong HU

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/02 ,  H01L24/03 ,  H01L2224/02381 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/0239 ,  H01L2924/01013 ,  H01L2224/05085 ,  H01L2224/03462 ,  H01L2224/0391

Abstract: A semiconductor device with a pad structure resistant to plasma damage includes: a main pad portion including main conductor units and main via units; a sub-pad portion including sub-conductor units and sub-via units; a pad bonding unit in direct contact with and in connection with a top main conductor unit, wherein the top main conductor unit is the main conductor unit formed in a top metal layer; and a bridge pad unit in direct contact with a top sub-conductor unit, wherein the top sub-conductor unit is the sub-conductor unit formed in the top metal layer. The bridge pad unit is in direct contact with the pad bonding unit. The main pad portion and sub-pad portion are located below the pad bonding unit and bridge pad unit respectively, and the main pad portion and the sub-pad portion are not in direct connection with each other.

公开(公告)号：US20250056853A1

公开(公告)日：2025-02-13

申请号：US18473417

申请日：2023-09-25

Applicant: Richtek Technology Corporation

Inventor： Wen-Wei LAI ,  Wu-Te WENG

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/40 ,  H01L29/808

Abstract: A junction field effect transistor device includes a substrate, a well region, a first top layer, a plurality of source/drain regions, a first isolation structure, a gate, and a plurality of first well slots. The substrate has a first conductivity type. The well region is embedded in the substrate. The well region has a second conductivity type. The first top layer is embedded in the well region. The first top layer has the first conductivity type. The source/drain regions are disposed on a top surface of the well region. The first isolation structure is adjacent to one of the source/drain regions. The gate is disposed on a top surface of the first top layer. The first well slots are disposed below the gate. A second-conductivity-type dopant concentration of the first well slots is lower than a second-conductivity-type dopant concentration of the well region.