公开(公告)号：US20240363570A1

公开(公告)日：2024-10-31

申请号：US18141456

申请日：2023-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jose Daniel Carlos Torres ,  Katleen Fajardo Timbol

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L23/31 ,  H01L23/4951 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05672 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11831 ,  H01L2224/13018 ,  H01L2224/13147 ,  H01L2224/16245

Abstract: A semiconductor package comprises an integrated circuit having a contact and a conductive bump directly attached to the contact. The conductive bump has a sidewall with a roughened surface. A leadframe is electrically coupled to the conductive bump. An integrated circuit package mold covers portions of the conductive bump and the lead frame, the roughened surface of the conductive bump is configured to interlock with the integrated circuit package mold. An electrically conductive adhesive couples the conductive bump to the lead frame. The conductive bump comprises copper in one arrangement. The roughened surface of the conductive bump includes grooves along grain boundaries that separate copper grains. The roughened surface of the conductive bump is formed by etching with a diluted sulfuric peroxide solution.

公开(公告)号：US20240363556A1

公开(公告)日：2024-10-31

申请号：US18139204

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/66 ,  H01Q1/50 ,  H01Q9/04

CPC classification number: H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01Q1/50 ,  H01Q9/0457 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/08147 ,  H01L2224/08267 ,  H01L2224/16267 ,  H01L2224/2929 ,  H01L2224/29499 ,  H01L2224/32267 ,  H01L2224/32268

Abstract: An antenna device includes an antenna on a substrate, a low-impedance electrostatic discharge (ESD) path for an ESD pulse from the antenna to a ground terminal, and a signal path between the antenna and either a signal terminal or an integrated circuit (IC) die. The ESD and signal paths may each include separate vias through the substrate. A capacitor may couple a signal to or from the antenna and the signal terminal (or IC die) but block low-frequency power (such as an ESD pulse). The ESD path has an electrical length of a quarter of the wavelength and so may present a high impedance to ground for the signal. The antenna device may include or be coupled to an IC die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US20240363512A1

公开(公告)日：2024-10-31

申请号：US18770126

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/80895 ,  H01L2225/06544 ,  H01L2924/0695

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

公开(公告)号：US20240363505A1

公开(公告)日：2024-10-31

申请号：US18765477

申请日：2024-07-08

Applicant: Taiwan Semicondutor Manufacturing Company, Ltd.

Inventor： Feng-Wei KUO ,  Wen-Shiang Liao

IPC: H01L23/495 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/49589 ,  H01L21/02422 ,  H01L21/31055 ,  H01L21/76832 ,  H01L23/29 ,  H01L23/49827 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/11 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2924/19041

Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

公开(公告)号：US20240363453A1

公开(公告)日：2024-10-31

申请号：US18140085

申请日：2023-04-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L21/66 ,  G01R31/28 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L21/78 ,  H01L24/05 ,  H01L2224/05553

Abstract: A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.

公开(公告)号：US20240363364A1

公开(公告)日：2024-10-31

申请号：US18769417

申请日：2024-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JEN-FU LIU ,  MING HUNG TSENG ,  YEN-LIANG LIN ,  LI-KO YEH ,  HUI-CHUN CHIANG ,  CHENG-CHIEH WU

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/2101 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2924/181 ,  H01L2924/37001

Abstract: A semiconductor structure includes a first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die; and a molding material encapsulating the first die, the first conductive vias, the second conductive vias and the third conductive vias. A first width of each of the plurality of first conductive vias, a second width of each of the plurality of second conductive vias and a third width of the plurality of third conductive vias are different from each other.

公开(公告)号：US12132019B2

公开(公告)日：2024-10-29

申请号：US18151622

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L21/561 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/06182 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/08225 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/80895 ,  H01L2224/83099 ,  H01L2224/8389 ,  H01L2224/92142 ,  H01L2225/06541 ,  H01L2225/06548

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US20240355783A1

公开(公告)日：2024-10-24

申请号：US18757428

申请日：2024-06-27

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

公开(公告)号：US20240355763A1

公开(公告)日：2024-10-24

申请号：US18761075

申请日：2024-07-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： En Hao HSU ,  Kuo Hwa TZENG ,  Chia-Pin CHEN ,  Chi Long TSAI

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/022 ,  H01L2224/02377 ,  H01L2224/13018

Abstract: An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.

公开(公告)号：US20240355738A1

公开(公告)日：2024-10-24

申请号：US18304869

申请日：2023-04-21

Applicant: Wolfspeed, Inc.

Inventor： Afshin Dadvand ,  Devarajan Balaraman

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/29 ,  H01L29/45

CPC classification number: H01L23/53219 ,  H01L23/291 ,  H01L23/293 ,  H01L23/53233 ,  H01L24/05 ,  H01L24/08 ,  H01L24/48 ,  H01L29/452 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/08113 ,  H01L2224/48245 ,  H01L2924/01004 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091

Abstract: Semiconductor devices and methods are provided. In one example, a semiconductor device includes an active region comprising one or more active semiconductor cells. The semiconductor device includes a metallization structure on the active region. The metallization structure includes beryllium.