Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit
    3.
    发明授权
    Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit 有权
    优化电源布线布局并生成半导体集成电路布线布局数据的方法和装置

    公开(公告)号:US06405354B1

    公开(公告)日:2002-06-11

    申请号:US09215239

    申请日:1998-12-18

    IPC分类号: G06F1750

    CPC分类号: G06F17/5077 G06F17/5072

    摘要: A program for generating layout data for a semiconductor integrated circuit analyzes a power network of individual modules in order to determine when an iterative layout process is complete. First, the individual modules are laid out and power supply wirings to the modules are laid out. Next, using cell size information about the cells within each of the modules, the cells of each module are temporarily arranged within the modules. Then, the power wirings and power supply terminals for each module are specified. A power network of each module is then sampled based on the cells, power wirings and power supply terminals of each module. Using the sample data, it is determined whether the modules and the power supply wirings to the modules need to be laid out again. The program may be executed on a CAD system.

    摘要翻译: 用于生成半导体集成电路的布局数据的程序分析各个模块的电力网络,以便确定迭代布局处理何时完成。 首先,布置各个模块,并布置电源线到模块。 接下来,使用关于每个模块内的小区的小区大小信息,每个模块的小区临时地布置在模块内。 然后,指定每个模块的电源配线和电源端子。 然后根据每个模块的单元,电源配线和电源端子对每个模块的电网进行采样。 使用样本数据,确定模块和电源配线是否需要重新排列。 该程序可以在CAD系统上执行。