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公开(公告)号：US11990905B1
公开(公告)日：2024-05-21
申请号：US18307647
申请日：2023-04-26
申请人： Rigetti & Co, LLC
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： G06N99/00 , G06N10/00 , H03K19/195
CPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.
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公开(公告)号：US12033032B2
公开(公告)日：2024-07-09
申请号：US17119089
申请日：2020-12-11
申请人： Rigetti & Co, LLC
发明人： Michael Justin Gerchick Scheer , Maxwell Benjamin Block , Benjamin Jacob Bloom , Matthew J. Reagor , Alexander Papageorge , Kamal Yadav , Nasser Alidoust , Colm Andrew Ryan , Shane Arthur Caldwell , Yuvraj Mohan , Anthony Polloreno , John Morrison Macaulay , Blake Robert Johnson
IPC分类号： G06F15/78 , G06F30/373 , G06F30/392 , G06F30/3947 , G06N10/40
CPC分类号： G06N10/40 , G06F15/7896 , G06F30/373 , G06F30/392 , G06F30/3947
摘要： In a general aspect, a quantum processor has a modular architecture. In some aspects, a modular quantum processor includes first and second quantum processor chips and a cap structure. The first quantum processor chip is supported on a substrate layer and includes a first plurality of qubit devices. The second quantum processor chip is supported on the substrate layer and includes a second plurality of qubit devices. The cap structure is supported on the first and second quantum processor chips and includes a coupler device that provides coupling between at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. In some instances, the coupler device is an active coupler device that is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.
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公开(公告)号：US20240146307A1
公开(公告)日：2024-05-02
申请号：US18307647
申请日：2023-04-26
申请人： Rigetti & Co, LLC
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： H03K19/195 , G06N10/00
CPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.
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公开(公告)号：US11875222B1
公开(公告)日：2024-01-16
申请号：US16134177
申请日：2018-09-18
申请人： Rigetti & Co, LLC
发明人： Matthew J. Reagor , Christopher Butler Osborn , Alexa Nitzan Staley , Sabrina Sae Byul Hong , Benjamin Jacob Bloom , Alexander Papageorge , Nasser Alidoust
摘要： In a general aspect, a method executed in a quantum computing system includes performing a calibration process in the quantum computing system to identify a value of a parameter of the quantum computing system. The method also includes analyzing a variation of the value in response to a change in a condition of the quantum computing system, thereby determining a stability of the parameter. The method additionally includes scheduling a recalibration of the parameter based on the stability of the parameter and executing a quantum algorithm in the quantum computing system based on the value of the parameter identified by the calibration process.
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公开(公告)号：US20240364345A1
公开(公告)日：2024-10-31
申请号：US18637081
申请日：2024-04-16
申请人： Rigetti & Co, LLC
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： H03K19/195 , G06N10/00
CPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.
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公开(公告)号：US20220231690A1
公开(公告)日：2022-07-21
申请号：US17410042
申请日：2021-08-24
申请人： Rigetti & Co, LLC
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.
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公开(公告)号：US11677402B2
公开(公告)日：2023-06-13
申请号：US17410042
申请日：2021-08-24
申请人： Rigetti & Co, LLC
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： G06N10/00 , H03K19/195
CPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.
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