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公开(公告)号：US20240112060A1
公开(公告)日：2024-04-04
申请号：US18465085
申请日：2023-09-11
发明人： Matthew J. Reagor , Thomas C. Bohdanowicz , David Rodriguez Perez , Eyob A. Sete , William J. Zeng
CPC分类号： G06N10/70 , H03M13/159 , H03M13/611
摘要： In a general aspect, a surface code syndrome measurement is performed on a superconducting quantum processing unit. In some implementations, the superconducting quantum processing unit is caused to apply a quantum error correction code including X-type and Z-type stabilizer check patches. Each of the X-type and Z-type stabilizer check patches includes a stabilizer check qubit device and data qubit devices of the superconducting quantum processing unit. Applying the quantum error correction code includes iteratively twirling the data qubit devices in a stabilizer check patch; and evolving the stabilizer check qubit device in the stabilizer check patch and the data qubit devices in the stabilizer check patch under an interaction Hamiltonian. The interaction Hamiltonian includes a plurality of terms interactions between the stabilizer check qubit device in the stabilizer check patch and a respective one of the data qubit devices in the stabilizer check patch.
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公开(公告)号：US20230394342A1
公开(公告)日：2023-12-07
申请号：US18155903
申请日：2023-01-18
申请人： Rigetti & Co, LLC
发明人： Benjamin Jacob Bloom , Shane Arthur Caldwell , Michael James Curtis , Matthew J. Reagor , Chad Tyler Rigetti , Eyob A. Sete , William J. Zeng , Peter Jonathan Karalekas , Nikolas Anton Tezak , Nasser Alidoust
IPC分类号： G06N10/00 , H03K19/195
CPC分类号： G06N10/00 , H03K19/195
摘要： In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.
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公开(公告)号：US20240146307A1
公开(公告)日：2024-05-02
申请号：US18307647
申请日：2023-04-26
申请人： Rigetti & Co, LLC
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： H03K19/195 , G06N10/00
CPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.
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公开(公告)号：US11593698B2
公开(公告)日：2023-02-28
申请号：US17338024
申请日：2021-06-03
申请人： Rigetti & Co, LLC
发明人： Benjamin Jacob Bloom , Shane Arthur Caldwell , Michael James Curtis , Matthew J. Reagor , Chad Tyler Rigetti , Eyob A. Sete , William J. Zeng , Peter Jonathan Karalekas , Nikolas Anton Tezak , Nasser Alidoust
IPC分类号： G06N10/00 , H03K19/195
摘要： In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.
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公开(公告)号：US11307242B1
公开(公告)日：2022-04-19
申请号：US17066187
申请日：2020-10-08
申请人： Rigetti & Co, LLC
摘要： In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.
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公开(公告)号：US20240364345A1
公开(公告)日：2024-10-31
申请号：US18637081
申请日：2024-04-16
申请人： Rigetti & Co, LLC
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： H03K19/195 , G06N10/00
CPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.
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公开(公告)号：US20220231690A1
公开(公告)日：2022-07-21
申请号：US17410042
申请日：2021-08-24
申请人： Rigetti & Co, LLC
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.
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公开(公告)号：US11990905B1
公开(公告)日：2024-05-21
申请号：US18307647
申请日：2023-04-26
申请人： Rigetti & Co, LLC
发明人： Eyob A. Sete , Nicolas Didier , Marcus Palmer da Silva , Chad Tyler Rigetti , Matthew J. Reagor , Shane Arthur Caldwell , Nikolas Anton Tezak , Colm Andrew Ryan , Sabrina Sae Byul Hong , Prasahnt Sivarajah , Alexander Papageorge , Deanna Margo Abrams
IPC分类号： G06N99/00 , G06N10/00 , H03K19/195
CPC分类号： H03K19/195 , G06N10/00
摘要： In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.
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公开(公告)号：US11977956B2
公开(公告)日：2024-05-07
申请号：US18155903
申请日：2023-01-18
申请人： Rigetti & Co, LLC
发明人： Benjamin Jacob Bloom , Shane Arthur Caldwell , Michael James Curtis , Matthew J. Reagor , Chad Tyler Rigetti , Eyob A. Sete , William J. Zeng , Peter Jonathan Karalekas , Nikolas Anton Tezak , Nasser Alidoust
IPC分类号： G06N10/70 , G06N10/00 , G06N10/40 , H03K19/195
CPC分类号： G06N10/70 , G06N10/00 , G06N10/40 , H03K19/195
摘要： In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.
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公开(公告)号：US11977113B1
公开(公告)日：2024-05-07
申请号：US18165272
申请日：2023-02-06
申请人： Rigetti & Co, LLC
CPC分类号： G01R31/2851 , G06N10/00
摘要： In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.
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