Hardware-Optimized Parity-check (HOP) Gates for Superconducting Surface Codes

    公开(公告)号:US20240112060A1

    公开(公告)日:2024-04-04

    申请号:US18465085

    申请日:2023-09-11

    IPC分类号: G06N10/70 H03M13/00 H03M13/15

    摘要: In a general aspect, a surface code syndrome measurement is performed on a superconducting quantum processing unit. In some implementations, the superconducting quantum processing unit is caused to apply a quantum error correction code including X-type and Z-type stabilizer check patches. Each of the X-type and Z-type stabilizer check patches includes a stabilizer check qubit device and data qubit devices of the superconducting quantum processing unit. Applying the quantum error correction code includes iteratively twirling the data qubit devices in a stabilizer check patch; and evolving the stabilizer check qubit device in the stabilizer check patch and the data qubit devices in the stabilizer check patch under an interaction Hamiltonian. The interaction Hamiltonian includes a plurality of terms interactions between the stabilizer check qubit device in the stabilizer check patch and a respective one of the data qubit devices in the stabilizer check patch.