公开(公告)号：US06578065B1

公开(公告)日：2003-06-10

申请号：US09405441

申请日：1999-09-23

申请人： Robert Aglietti ,  Tomas G. Rokicki ,  Rajiv Gupta

发明人： Robert Aglietti ,  Tomas G. Rokicki ,  Rajiv Gupta

IPC分类号： G06F900

CPC分类号： G06F9/4881 ,  G06F9/3851

摘要： A system and method for controlling the scheduling of threads in a multi-thread processor system. The multi-thread processor system has a multi-thread processor, a main memory, a cache memory, and a thread scheduler. Information is sent from the cache memory to the thread scheduler for determining which thread the processor is going to execute. The thread scheduler calculates or maintains a figure of merit for each thread executing on the processor. The figure of merit determines which thread to switch to when the current or previous thread has a long latency. The figure of merit define the execution environment as measured by the performance of the cache memory. The figure of merit can be the owner of a particular thread, the number of data lines accessed by a particular thread which resides in the cache, the number of times a particular thread has hit in the cache over a specified time interval, the thread that installed the data or the thread that was used most recently.

摘要翻译： 一种用于控制多线程处理器系统中的线程调度的系统和方法。 多线程处理器系统具有多线程处理器，主存储器，高速缓冲存储器和线程调度器。 信息从高速缓冲存储器发送到线程调度器，以确定处理器将执行哪个线程。 线程调度器计算或维护在处理器上执行的每个线程的品质因数。 当当前或之前的线程具有较长的延迟时，品质因数决定了切换到哪个线程。 品质因数定义了由高速缓冲存储器的性能测量的执行环境。 品质因数可以是特定线程的所有者，由驻留在缓存中的特定线程访问的数据线的数量，特定线程在指定时间间隔内在高速缓存中的次数，线程 安装了最近使用的数据或线程。

公开(公告)号：US06453389B1

公开(公告)日：2002-09-17

申请号：US09340279

申请日：1999-06-25

申请人： Marcelo Weinberger ,  Tomas G. Rokicki ,  Gadiel Seroussi ,  Rajiv Gupta ,  Neri Merhav ,  Joesp M. Ferrandiz

发明人： Marcelo Weinberger ,  Tomas G. Rokicki ,  Gadiel Seroussi ,  Rajiv Gupta ,  Neri Merhav ,  Joesp M. Ferrandiz

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F2212/6026

摘要： The method of prefetching data into cache to minimize CPU stall time uses a rough predictor to make rough predictions about what cache lines will be needed next by the CPU. The address difference generator uses the rough prediction and the actual cache miss address to determine the address difference. The prefetch engine builds a data structure to represent address differences and weights them according to the accumulated stall time produced by the cache misses given that the corresponding address is not prefetched. This stall time is modeled as a loss function of the form: L = ∑ j = 0 n ⁢   ⁢ L ⁢   ⁢ ( x j ) L ⁢   ⁢ ( x j ) = ∑ i = 0 sl ⁡ ( j ) - 1 ⁢   ⁢ C i ⁢   ⁢ ( b j - i , x j ) The weights in the data structure change as the prefetch engine learns more information. The prefetch engine's goal is to predict the cache line needed and prefetch before the CPU requests it.

摘要翻译： 将数据预取到缓存中以最小化CPU停顿时间的方法使用粗略的预测器来粗略地预测CPU将需要什么高速缓存行。 地址差产生器使用粗略预测和实际高速缓存未命中地址来确定地址差异。 预取引擎构建数据结构以表示地址差异，并根据缓存未命中产生的累积停顿时间来加权它们，因为相应地址未被预取。 该失速时间被建模为形式的损失函数：数据结构中的权重随着预取引擎学习更多信息而改变。 预取引擎的目标是在CPU请求之前预测所需的高速缓存行和预取。

公开(公告)号：US06389514B1

公开(公告)日：2002-05-14

申请号：US09277006

申请日：1999-03-25

申请人： Tomas G. Rokicki

发明人： Tomas G. Rokicki

IPC分类号： G06F1208

CPC分类号： G06F12/0215

摘要： The present invention provides a method and an apparatus for addressing a main memory unit in a computer system which results in improved page hit rate and reduced memory latency by only keeping open some recently used pages and speculatively closing the rest of the pages in the main memory unit. In a computer system with 64 banks and 2 CPUs, only 8 banks may be kept open and the remaining 56 banks are kept closed. Keeping only 8 banks open will not reduce the page hit frequency significantly, but will allow most accesses that are not page hits to access banks that are already closed, so that they are not slowed down by open banks. Thus, the page hit rate is increased and the miss rate is reduced.

摘要翻译： 本发明提供了一种用于寻址计算机系统中的主存储器单元的方法和装置，其通过仅保持打开一些最近使用的页面并且推测性地关闭主存储器中的其余页面而导致改进的页命中率和减少的存储器等待时间 单元。 在拥有64个银行和2个CPU的计算机系统中，只有8个银行可能保持开放，其余56个银行将被关闭。 只有8家银行开放不会显着降低页面命中频率，但是允许大多数不是页面访问的访问访问已经关闭的银行，以便它们不会被开放银行放慢。 因此，页面命中率增加，丢失率降低。

公开(公告)号：US6070227A

公开(公告)日：2000-05-30

申请号：US963673

申请日：1997-10-31

申请人： Tomas G. Rokicki

发明人： Tomas G. Rokicki

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0215 ,  G06F12/0882

摘要： A main memory indexing scheme optimizes consecutive page hits in computer systems having a main memory system and a cache memory. In accordance with the present invention, one or more bank select bits required by the main memory system are formed from one or more of the address bits that are used by the cache memory as the tag field. Preferably, the lower-order bits of the tag field are used. To increase the page hit rate even further, additional bank select bits are formed from the address bits immediately above the bits used to access columns. In one embodiment of the present invention, address bits are simply mapped to bank bits using a one-to-one correspondence. In another embodiment, address bits from the tag field and address bits immediately above the column bits are combined using a function such as an exclusive-OR operation or an addition operation, with the result of the function provided to the bank select bits. The present invention greatly improves the page hit rate of computer systems, while requiring few additional resources.

摘要翻译： 主存储器索引方案优化具有主存储器系统和高速缓冲存储器的计算机系统中的连续页面命中。 根据本发明，由主存储器系统所需的一个或多个存储体选择位由高速缓冲存储器用作标签字段的一个或多个地址位形成。 优选地，使用标签字段的低位。 为了进一步提高页面命中率，从位于用于访问列的位之上的地址位形成额外的存储体选择位。 在本发明的一个实施例中，使用一对一对应关系将地址位简单地映射到存储体位。 在另一个实施例中，使用诸如异或运算或加法运算的功能，将功能的结果提供给存储体选择位来组合来自标签字段的地址位和位位之上的地址位。 本发明大大提高了计算机系统的页面命中率，同时需要少量额外的资源。