公开(公告)号：US20050240892A1

公开(公告)日：2005-10-27

申请号：US11156319

申请日：2005-06-18

申请人： Robert Broberg ,  Jonathan Byrn ,  Gary Delp ,  Michael Eneboe ,  Gary McClannahan ,  George Nation ,  Paul Reuland ,  Thomas Sandoval ,  Matthew Wingren

发明人： Robert Broberg ,  Jonathan Byrn ,  Gary Delp ,  Michael Eneboe ,  Gary McClannahan ,  George Nation ,  Paul Reuland ,  Thomas Sandoval ,  Matthew Wingren

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505

摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

摘要翻译： 本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。 输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。 输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。 切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。 这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。 这些设计经过其他工具的合格，测试和验证。 这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。 该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。 这些工具也具有迭代模式和全局模式。 在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。 在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。 这套生成工具生成设计视图，包括用于制造铸造的合格网表。

公开(公告)号：US20070033557A1

公开(公告)日：2007-02-08

申请号：US11199434

申请日：2005-08-08

申请人： Jonathan Byrn ,  Matthew Wingren ,  Paul Reuland

发明人： Jonathan Byrn ,  Matthew Wingren ,  Paul Reuland

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/50 ,  G06F2217/06 ,  G06F2217/62

摘要： A method for creating constraints for integrated circuit design closure is provided. Design specifications are captured before a design flow is started. The design specifications are checked for compatibility with the design flow. The design specifications are stored in a database. Output transforms are applied to the design specifications to create orthogonal constraint sets which are tuned for both a specific tool and a positional use of the specific tool within the design flow.

摘要翻译： 提供了一种用于创建集成电路设计闭合的约束的方法。 设计规范在设计流程开始之前被捕获。 检查设计规格与设计流程的兼容性。 设计规范存储在数据库中。 将输出变换应用于设计规范，以创建针对设计流程中特定工具和特定工具的位置使用进行调整的正交约束集。

公开(公告)号：US20050062495A1

公开(公告)日：2005-03-24

申请号：US10664137

申请日：2003-09-17

申请人： Jonathan Byrn ,  James Jensen ,  Matthew Wingren

发明人： Jonathan Byrn ,  James Jensen ,  Matthew Wingren

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L27/10 ,  H02H3/00

CPC分类号： G06F17/5045 ,  H01L27/0203

摘要： A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

摘要翻译： 标准化的硅平台芯片具有一个具有围绕岛屿的未连接晶体管阵列的衬底表面。 这些岛具有在每个岛内可互连的电路元件，以便为每个岛形成多个不同的电路功能。 各种电路功能包括应用功能和时钟功能。 互连层沉积在衬底表面上以互连每个岛内的电路元件以完成不同的电路功能。 各种电路功能包括至少包括门，触发器，时钟树和振荡器的不同级别的集成。 不同的电路功能可定制连接到未连接的晶体管阵列，以为标准化的硅平台芯片形成标准时钟资源。

公开(公告)号：US20060282808A1

公开(公告)日：2006-12-14

申请号：US11151043

申请日：2005-06-13

申请人： Jonathan Byrn ,  Matthew Wingren

发明人： Jonathan Byrn ,  Matthew Wingren

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e.g., clock property information, clock domain crossing information, and clock relationship specification. The tool and method embodied therein validates the clocking parameters of the design requirements with the resource definitions and invokes errors if the parameters are not realizable. Once the desired clocking parameters are consistent with the actual clocking parameters, correct physical optimization constraints and timing constraints are generated for the clocks. An iterative process can achieve correct and minimal clocking constraints.

摘要翻译： 输入预期半导体产品的设计要求和半导体平台的资源定义的电子设计自动化工具，装置，方法和程序产品。 根据设计要求和资源定义，导出专门针对时钟的参数，例如时钟属性信息，时钟域交叉信息和时钟关系规范。 其中包含的工具和方法使用资源定义来验证设计要求的时钟参数，如果参数不可实现，则调用错误。 一旦所需的时钟参数与实际时钟参数一致，则会为时钟生成正确的物理优化约束和时序约束。 迭代过程可以实现正确和最小的时钟约束。