公开(公告)号：US20050240892A1

公开(公告)日：2005-10-27

申请号：US11156319

申请日：2005-06-18

申请人： Robert Broberg ,  Jonathan Byrn ,  Gary Delp ,  Michael Eneboe ,  Gary McClannahan ,  George Nation ,  Paul Reuland ,  Thomas Sandoval ,  Matthew Wingren

发明人： Robert Broberg ,  Jonathan Byrn ,  Gary Delp ,  Michael Eneboe ,  Gary McClannahan ,  George Nation ,  Paul Reuland ,  Thomas Sandoval ,  Matthew Wingren

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505

摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

摘要翻译： 本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。 输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。 输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。 切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。 这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。 这些设计经过其他工具的合格，测试和验证。 这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。 该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。 这些工具也具有迭代模式和全局模式。 在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。 在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。 这套生成工具生成设计视图，包括用于制造铸造的合格网表。

公开(公告)号：US20070033557A1

公开(公告)日：2007-02-08

申请号：US11199434

申请日：2005-08-08

申请人： Jonathan Byrn ,  Matthew Wingren ,  Paul Reuland

发明人： Jonathan Byrn ,  Matthew Wingren ,  Paul Reuland

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/50 ,  G06F2217/06 ,  G06F2217/62

摘要： A method for creating constraints for integrated circuit design closure is provided. Design specifications are captured before a design flow is started. The design specifications are checked for compatibility with the design flow. The design specifications are stored in a database. Output transforms are applied to the design specifications to create orthogonal constraint sets which are tuned for both a specific tool and a positional use of the specific tool within the design flow.

摘要翻译： 提供了一种用于创建集成电路设计闭合的约束的方法。 设计规范在设计流程开始之前被捕获。 检查设计规格与设计流程的兼容性。 设计规范存储在数据库中。 将输出变换应用于设计规范，以创建针对设计流程中特定工具和特定工具的位置使用进行调整的正交约束集。

公开(公告)号：US20050062495A1

公开(公告)日：2005-03-24

申请号：US10664137

申请日：2003-09-17

申请人： Jonathan Byrn ,  James Jensen ,  Matthew Wingren

发明人： Jonathan Byrn ,  James Jensen ,  Matthew Wingren

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L27/10 ,  H02H3/00

CPC分类号： G06F17/5045 ,  H01L27/0203

摘要： A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

摘要翻译： 标准化的硅平台芯片具有一个具有围绕岛屿的未连接晶体管阵列的衬底表面。 这些岛具有在每个岛内可互连的电路元件，以便为每个岛形成多个不同的电路功能。 各种电路功能包括应用功能和时钟功能。 互连层沉积在衬底表面上以互连每个岛内的电路元件以完成不同的电路功能。 各种电路功能包括至少包括门，触发器，时钟树和振荡器的不同级别的集成。 不同的电路功能可定制连接到未连接的晶体管阵列，以为标准化的硅平台芯片形成标准时钟资源。

公开(公告)号：US20060282808A1

公开(公告)日：2006-12-14

申请号：US11151043

申请日：2005-06-13

申请人： Jonathan Byrn ,  Matthew Wingren

发明人： Jonathan Byrn ,  Matthew Wingren

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e.g., clock property information, clock domain crossing information, and clock relationship specification. The tool and method embodied therein validates the clocking parameters of the design requirements with the resource definitions and invokes errors if the parameters are not realizable. Once the desired clocking parameters are consistent with the actual clocking parameters, correct physical optimization constraints and timing constraints are generated for the clocks. An iterative process can achieve correct and minimal clocking constraints.

摘要翻译： 输入预期半导体产品的设计要求和半导体平台的资源定义的电子设计自动化工具，装置，方法和程序产品。 根据设计要求和资源定义，导出专门针对时钟的参数，例如时钟属性信息，时钟域交叉信息和时钟关系规范。 其中包含的工具和方法使用资源定义来验证设计要求的时钟参数，如果参数不可实现，则调用错误。 一旦所需的时钟参数与实际时钟参数一致，则会为时钟生成正确的物理优化约束和时序约束。 迭代过程可以实现正确和最小的时钟约束。

公开(公告)号：US07412678B2

公开(公告)日：2008-08-12

申请号：US10859874

申请日：2004-06-02

申请人： Juergen Lahner ,  Srinivas Adusumalli ,  Jonathan Byrn

发明人： Juergen Lahner ,  Srinivas Adusumalli ,  Jonathan Byrn

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F1/12

摘要： A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path between synchronous clock domains is defined as a false path in the integrated circuit design, then reporting a fatal violation.

摘要翻译： 公开了一种用于管理同步和异步时钟域交叉的方法和计算机程序，其包括以下步骤：（a）作为输入接收集成电路设计; （b）识别集成电路设计中的同步时钟域和异步时钟域之间的路径之间的路径; 和（c）如果在集成电路设计中将同步时钟域之间的路径定义为虚路径，则报告致命违规。

公开(公告)号：US07494842B2

公开(公告)日：2009-02-24

申请号：US11286546

申请日：2005-11-23

申请人： Jonathan Byrn

发明人： Jonathan Byrn

IPC分类号： H01L51/40

CPC分类号： H01L21/76838 ,  H01L23/525 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer. Neighboring interconnect layers separated by planar vias may include communication lines that are perpendicularly oriented with respect to each of the neighboring interconnect layers. The nanotube structure may be chosen from a group comprising a polymer, carbon, and a composite material. A carbon nanotube film may be patterned in a metal layer to form the plurality of nanotube structures. A sputtered planar process may be performed across a trench of electrodes to create the carbon nanotube structures.

摘要翻译： 公开了可编程纳米管互连。 在一个实施例中，一种方法包括使用多个纳米管结构形成互连层，并且基于施加到互连层中的多个纳米管结构中的至少一个的电流自动地改变集成电路的路径。 由平面通孔分隔的相邻互连层可以包括相对于每个相邻互连层垂直取向的通信线。 纳米管结构可以选自包含聚合物，碳和复合材料的组。 碳纳米管膜可以在金属层中图案化以形成多个纳米管结构。 溅射的平面工艺可以跨越电极的沟槽进行，以产生碳纳米管结构。

公开(公告)号：US20070125999A1

公开(公告)日：2007-06-07

申请号：US11286558

申请日：2005-11-23

申请人： Jonathan Byrn

发明人： Jonathan Byrn

IPC分类号： H01L29/08

CPC分类号： H01L23/53276 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

摘要： Configurable power segmentation using a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer in an integrated circuit, and coupling a power region in the transistor layer to at least one power source based on a state of the nanotube structure. Nanotube material may be sputtered over a plurality of layers to form the nanotube structure. The nanotube structure may be curved to flex to a conductive surface when a current is applied to the nanotube structure. The power region may be coupled with at least two power sources that are concatenated together to provide cascaded current to the power region. One or more power regions in the integrated circuit may be enable based on the patterning the nanotube structure and the coupling of the power region to at least one power source.

摘要翻译： 公开了使用纳米管结构的可配置功率分割。 在一个实施例中，一种方法包括图案化集成电路中与晶体管层相邻的纳米管结构，并且基于纳米管结构的状态将晶体管层中的功率区域耦合到至少一个电源。 纳米管材料可以溅射在多个层上以形成纳米管结构。 当向纳米管结构施加电流时，纳米管结构可以弯曲以弯曲到导电表面。 功率区域可以与连接在一起的至少两个电源耦合以向功率区域提供级联电流。 基于图案化纳米管结构和功率区域与至少一个电源的耦合，集成电路中的一个或多个功率区域可以被实现。

公开(公告)号：US08209573B2

公开(公告)日：2012-06-26

申请号：US12341825

申请日：2008-12-22

申请人： Jeff S. Brown ,  Mark F. Turner ,  Jonathan Byrn

发明人： Jeff S. Brown ,  Mark F. Turner ,  Jonathan Byrn

IPC分类号： G01R31/28 ,  H03K3/289

CPC分类号： G01R31/318536

摘要： A sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.

摘要翻译： 具有主级和从级的顺序元件以及测试具有扫描链和IC的IC的方法。 在一个实施例中，顺序元件包括输入扫描多路复用器，其被配置为响应于扫描使能输入和耦合到从站的扫描输出驱动器将顺序元件置于功能模式或扫描模式，并且被配置为提供扫描输出 当顺序元件处于扫描模式时，扫描输出驱动器耦合到用于负电压源的反相扫描使能输入。

公开(公告)号：US07340700B2

公开(公告)日：2008-03-04

申请号：US11140392

申请日：2005-05-27

申请人： Steven Emerson ,  Jonathan Byrn ,  Donald Gabrielson ,  Gary Lippert

发明人： Steven Emerson ,  Jonathan Byrn ,  Donald Gabrielson ,  Gary Lippert

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/31704 ,  G01R31/318555

摘要： A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

摘要翻译： 用于集成电路布局模式中RTL测试插入的系统包括核心模块，测试包装器和智能包装器。 核心模块描述了由逻辑元件定义的功能，逻辑元件，输入引脚和输出引脚之间的互连。 测试包装器适用于封装核心模块并创建表示核心模块的测试引脚。 智能包装器适用于封装测试包装器，并将测试引脚分配到非断言状态。 智能包装器适用于将一个断言置于一个或多个测试引脚上，用于集成电路布局图案的静态或动态测试。

公开(公告)号：US20070114517A1

公开(公告)日：2007-05-24

申请号：US11286557

申请日：2005-11-23

申请人： Jonathan Byrn

发明人： Jonathan Byrn

IPC分类号： H01L29/08 ,  H01L35/24 ,  H01L51/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L51/0048 ,  H01L51/0579 ,  Y10S977/938

摘要： Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to the conductive surface. A current may be applied to the nanotube structure to couple the nanotube structure to the conductive surface. The nanotube structure may be formed from a material chosen from one or more of a polymer, carbon, and a composite material. The group of transistors may be enabled during an activation sequence of the integrated circuit. In addition, one or more transistors of the group of transistors may be disengaged from the one or more power sources (e.g., to minimize leakage) when the nanotube structure is decoupled from the conductive surface.

摘要翻译： 公开了使用纳米管结构的可编程功率管理。 在一个实施例中，一种方法包括当处理命令时将集成电路的纳米管结构耦合到导电表面，并且基于将纳米管结构耦合到导电表面来启用集成电路的一组晶体管。 可以将电流施加到纳米管结构以将纳米管结构耦合到导电表面。 纳米管结构可以由选自聚合物，碳和复合材料中的一种或多种的材料形成。 晶体管组可以在集成电路的激活序列期间使能。 此外，当纳米管结构与导电表面分离时，该组晶体管中的一个或多个晶体管可以与一个或多个电源脱离（例如，以最小化泄漏）。