公开(公告)号：US4794570A

公开(公告)日：1988-12-27

申请号：US165456

申请日：1988-03-01

申请人： Robert C. Rose ,  Jash Patel

发明人： Robert C. Rose ,  Jash Patel

IPC分类号： H03K19/177 ,  G11C13/00

CPC分类号： H03K19/1772

摘要： A programmable logic array includes a decoder section and an encoder section connected by a plurality of minterm conductors. The decoder section receives a plurality of input signals and in response selects appropriate ones of the minterm conductors. The selection of the minterm conductors enable the encoder selection to transmit a plurality of output signal on respective output conductors. The decoder and encoder sections include a plurality of stages, each controlling a minterm conductor and output conductor in response to the input signals and the selection of the minterm conductor. The stages include control transistors that are connected between a node, to which the respective minterm and output conductors are connected, and switches which enable and disable the control transistors. The nodes are initially precharged while the switches disable the respective transistors. After precharge, the switches enable the transistors in the decoder and encoder section respectively. A self timing circuit controls the switches to ensure that the switches are correctly timed.

公开(公告)号：US4914633A

公开(公告)日：1990-04-03

申请号：US288671

申请日：1988-12-22

申请人： Robert Rose ,  Jash Patel

发明人： Robert Rose ,  Jash Patel

IPC分类号： H03K19/177

CPC分类号： H03K19/1772

摘要： A programmable logic array includes a decoder section and an encoder section connected by a plurality of minterm conductors. The decoder section receives a plurality of input signals and in response selects appropriate ones of the minterm conductors. The selection of the minterm conductors enable the encoder selection to transmit a plurality of output signal on respective output conductors. The decoder and encoder sections include a plurality of stages, each controlling a minterm conductor and output conductor in response to the input signals and the selection of the minterm conductor. The stages include control transistors that are connected between a node, to which the respective minterm and output conductors are connected, and switches which enable and disable the control transistors. The nodes are initially precharged while the switches disable the respective transistors. After precharge, the switches enable the transistors in the decoder and encoder section respectively. A self timing circuit controls the switches to ensure that the switches are correctly timed.

摘要翻译： 可编程逻辑阵列包括由多个微型导体连接的解码器部分和编码器部分。 解码器部分接收多个输入信号，并且响应于选择适当的最小导体。 最小导体的选择使编码器选择能够在相应的输出导体上传输多个输出信号。 解码器和编码器部分包括多个级，每个级响应于输入信号和最小导体的选择而控制最小导体和输出导体。 这些级包括连接在相应的最小端子和输出导体所连接的节点之间的控制晶体管以及启用和禁用控制晶体管的开关。 节点最初被预充电，而开关禁用相应的晶体管。 在预充电之后，开关分别使能解码器和编码器部分中的晶体管。 自定时电路控制开关，以确保开关正确定时。