ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
    1.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME 有权
    静电放电保护装置及其制造方法

    公开(公告)号:US20070170512A1

    公开(公告)日:2007-07-26

    申请号:US11275638

    申请日:2006-01-20

    IPC分类号: H01L23/62

    摘要: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

    摘要翻译: 公开了一种硅控制整流器,制造硅控制整流器的方法和使用硅控整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体,其与绝缘体上硅衬底的掩埋氧化物层直接物理接触,硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极,其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

    SUBSTRATE TRIGGERING FOR ESD PROTECTION IN SOI
    2.
    发明申请
    SUBSTRATE TRIGGERING FOR ESD PROTECTION IN SOI 有权
    SOI中ESD保护的衬底触发

    公开(公告)号:US20070253126A1

    公开(公告)日:2007-11-01

    申请号:US11380525

    申请日:2006-04-27

    IPC分类号: H02H9/00

    CPC分类号: H01L27/0266

    摘要: Electrostatic discharge (ESD) protection device and process for protecting a conventional FET. The device includes at least one FET body forming a resistance, and a triggering circuit coupled to a protection FET and the resistance. The resistance raises a voltage of the at least one body, such that the protection FET is triggered at a voltage lower than the conventional FET.

    摘要翻译: 静电放电(ESD)保护装置和保护常规FET的工艺。 该器件包括至少一个形成电阻的FET体,以及耦合到保护FET和电阻的触发电路。 电阻提高至少一个体的电压,使得保护FET在比常规FET低的电压下被触发。

    AN ESD PROTECTION POWER CLAMP FOR SUPPRESSING ESD EVENTS OCCURRING ON POWER SUPPLY TERMINALS
    4.
    发明申请
    AN ESD PROTECTION POWER CLAMP FOR SUPPRESSING ESD EVENTS OCCURRING ON POWER SUPPLY TERMINALS 失效
    用于抑制电源端子发生ESD事件的ESD保护电源

    公开(公告)号:US20060039093A1

    公开(公告)日:2006-02-23

    申请号:US10711085

    申请日:2004-08-20

    IPC分类号: H02H9/00

    CPC分类号: H01L27/0266

    摘要: An ESD protection power clamp for suppressing ESD events. A clamping transistor having power source connections connected across the power supply terminals of an integrated circuit is connected to clamp the voltage during an ESD event. An RC timing circuit defines a time interval where ESD voltage for triggering the FET out of conduction. An inverter circuit connects the RC and timing circuit to the clamping FET. A dynamic feedback transistor is connected in series with one stage of the inverter and the power supply. During an ESD event, the feedback transistor delays the time for disabling the FET transistor, providing increased immunity against mistriggering of the clamping transistor, and forces the circuit to reset following the mistrigger event.

    摘要翻译: 用于抑制ESD事件的ESD保护电源钳。 具有连接在集成电路的电源端子上的电源连接的钳位晶体管被连接以在ESD事件期间钳位电压。 RC定时电路定义用于触发FET导通的ESD电压的时间间隔。 逆变器电路将RC和定时电路连接到钳位FET。 动态反馈晶体管与逆变器和电源的一级串联连接。 在ESD事件期间,反馈晶体管延迟了禁止FET晶体管的时间,提供了抵抗钳位晶体管失谐的增强的抗扰性,并迫使电路在雾触发器事件之后复位。