公开(公告)号：US06922349B2

公开(公告)日：2005-07-26

申请号：US10864238

申请日：2004-06-09

申请人： Robert L. Barry ,  Peter F. Croce ,  Steven M. Eustis ,  Yabin Wang

发明人： Robert L. Barry ,  Peter F. Croce ,  Steven M. Eustis ,  Yabin Wang

IPC分类号： G11C17/12 ,  G11C17/00 ,  G11C5/06

CPC分类号： G11C17/12

摘要： A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

摘要翻译： 只读存储器（ROM）单元阵列的方法和结构具有连接到互补位线的第一晶体管的第一漏极和第二晶体管的第二漏极，第二晶体管连接到真位线和第二晶体管的第二漏极。 第一晶体管还包括第一源极，第二晶体管包括第二源极。 第一个源或第二个源到地面的连接将ROM单元编程。 利用本发明，只有第一源或第二源连接到地，而另一个与电连接绝缘。 此外，源极与地的连接包括在制造第一晶体管和第二晶体管期间形成的电连接。

公开(公告)号：US06778419B2

公开(公告)日：2004-08-17

申请号：US10063212

申请日：2002-03-29

申请人： Robert L. Barry ,  Peter F. Croce ,  Steven M. Eustis ,  Yabin Wang

发明人： Robert L. Barry ,  Peter F. Croce ,  Steven M. Eustis ,  Yabin Wang

IPC分类号： G11C1700

CPC分类号： G11C17/12

摘要： A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

摘要翻译： 只读存储器（ROM）单元阵列的方法和结构具有连接到互补位线的第一晶体管的第一漏极和第二晶体管的第二漏极，第二晶体管连接到真位线和第二晶体管的第二漏极。 第一晶体管还包括第一源极，第二晶体管包括第二源极。 第一个源或第二个源到地面的连接将ROM单元编程。 利用本发明，只有第一源或第二源连接到地，而另一个与电连接绝缘。 此外，源极与地的连接包括在制造第一晶体管和第二晶体管期间形成的电连接。

公开(公告)号：US06721927B2

公开(公告)日：2004-04-13

申请号：US10063213

申请日：2002-03-29

申请人： Peter F. Croce ,  Steven M. Eustis ,  Yabin Wang

发明人： Peter F. Croce ,  Steven M. Eustis ,  Yabin Wang

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F2217/78 ,  G11C17/10

摘要： A method of designing an integrated circuit chip includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics.

摘要翻译： 设计集成电路芯片的方法包括：准备具有第一功率消耗率的第一宏，准备具有与第一功率消耗率不同的第二功率消耗率的第二宏，设计所述电路，测量所述电路的性能特性 ，而将第二个宏代替第一个宏来提高性能特征。 第一个宏和第二个宏具有相同的功能，器件，表面积大小，外部布线图形和时序特性。

公开(公告)号：US20050007809A1

公开(公告)日：2005-01-13

申请号：US10864238

申请日：2004-06-09

申请人： Robert L. Barry ,  Peter Croce ,  Steven Eustis ,  Yabin Wang

发明人： Robert L. Barry ,  Peter Croce ,  Steven Eustis ,  Yabin Wang

IPC分类号： G11C17/12 ,  G11C17/00

CPC分类号： G11C17/12

摘要： A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.