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公开(公告)号：US06922349B2
公开(公告)日：2005-07-26
申请号：US10864238
申请日：2004-06-09
申请人： Robert L. Barry , Peter F. Croce , Steven M. Eustis , Yabin Wang
发明人： Robert L. Barry , Peter F. Croce , Steven M. Eustis , Yabin Wang
CPC分类号： G11C17/12
摘要： A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.
摘要翻译： 只读存储器（ROM）单元阵列的方法和结构具有连接到互补位线的第一晶体管的第一漏极和第二晶体管的第二漏极，第二晶体管连接到真位线和第二晶体管的第二漏极。 第一晶体管还包括第一源极，第二晶体管包括第二源极。 第一个源或第二个源到地面的连接将ROM单元编程。 利用本发明，只有第一源或第二源连接到地，而另一个与电连接绝缘。 此外，源极与地的连接包括在制造第一晶体管和第二晶体管期间形成的电连接。
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公开(公告)号：US06778419B2
公开(公告)日：2004-08-17
申请号：US10063212
申请日：2002-03-29
申请人： Robert L. Barry , Peter F. Croce , Steven M. Eustis , Yabin Wang
发明人： Robert L. Barry , Peter F. Croce , Steven M. Eustis , Yabin Wang
IPC分类号： G11C1700
CPC分类号： G11C17/12
摘要： A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.
摘要翻译： 只读存储器（ROM）单元阵列的方法和结构具有连接到互补位线的第一晶体管的第一漏极和第二晶体管的第二漏极，第二晶体管连接到真位线和第二晶体管的第二漏极。 第一晶体管还包括第一源极，第二晶体管包括第二源极。 第一个源或第二个源到地面的连接将ROM单元编程。 利用本发明，只有第一源或第二源连接到地，而另一个与电连接绝缘。 此外，源极与地的连接包括在制造第一晶体管和第二晶体管期间形成的电连接。
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3.发明授权Substituting high performance and low power macros in integrated circuit chips 失效在集成电路芯片中代替高性能和低功耗宏公开(公告)号：US06721927B2
公开(公告)日：2004-04-13
申请号：US10063213
申请日：2002-03-29
申请人： Peter F. Croce , Steven M. Eustis , Yabin Wang
发明人： Peter F. Croce , Steven M. Eustis , Yabin Wang
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/78 , G11C17/10
摘要： A method of designing an integrated circuit chip includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics.
摘要翻译： 设计集成电路芯片的方法包括：准备具有第一功率消耗率的第一宏，准备具有与第一功率消耗率不同的第二功率消耗率的第二宏，设计所述电路，测量所述电路的性能特性 ，而将第二个宏代替第一个宏来提高性能特征。 第一个宏和第二个宏具有相同的功能，器件，表面积大小，外部布线图形和时序特性。
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4.发明授权公开(公告)号：US06600673B1
公开(公告)日：2003-07-29
申请号：US10248599
申请日：2003-01-31
申请人： Peter F. Croce , Steven M. Eustis , Ronald A. Piro
发明人： Peter F. Croce , Steven M. Eustis , Ronald A. Piro
IPC分类号： G11C1712
CPC分类号： G11C17/12 , G06F17/5045 , G11C17/18
摘要： A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and slave latches to one another. The first latch and the second latch include a write bitline connection that is permanently connected to a fixed voltage source to permanently program the first latch and the second latch to permanent ROM values.
摘要翻译： 一种用于一对只读存储器（ROM）单元的方法和结构，其具有连接到第一锁存器的第一锁存器和第二锁存器。 第一个锁存器和第二个锁存器作为主和从锁存器相互锁定。 第一锁存器和第二锁存器包括永久连接到固定电压源的写位线连接，以将第一锁存器和第二锁存器永久编程为永久ROM值。
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公开(公告)号：US06944075B1
公开(公告)日：2005-09-13
申请号：US10905451
申请日：2005-01-05
IPC分类号： G11C7/00
CPC分类号： G11C29/808 , G11C11/41 , G11C29/816
摘要： A method of assigning bits to redundant regions for variable bit redundancy region boundaries in a compliable memory such as a 1-port SRAM is provided. Methods include allocating bits between the redundant regions in nearly equal proportions while minimizing the amount of chip real estate consumed by the memory. Methods also includes allocating bits in equal portions between redundant regions while occupying slightly more memory chip real estate. Methods also allocate bits into redundant regions with a simplified procedure which may or may not allocate bits into the redundant regions in equal proportions. All of the methods allow the total number of memory bits in the complied memory to be re-defined while maintaining the same allocation characteristics for each method. Accordingly, the methods allow efficient use of redundant memory bits while also conserving chip real estate or offering simplified allocation steps.
摘要翻译： 提供了一种将比特分配给诸如1端口SRAM的可复制存储器中的可变位冗余区域边界的冗余区域的方法。 方法包括以几乎相等的比例在冗余区域之间分配比特，同时最小化存储器消耗的芯片空间的量。 方法还包括在冗余区域之间相等分配比特，同时占据稍微更多的存储器芯片空间。 方法还使用简化的过程将比特分配到冗余区域中，这可以或可以不以相等比例将比特分配到冗余区域中。 所有这些方法允许重新定义编译存储器中的存储器位的总数，同时为每种方法保持相同的分配特性。 因此，这些方法允许有效地使用冗余存储器位，同时还节省芯片空间或提供简化的分配步骤。
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公开(公告)号：US5920222A
公开(公告)日：1999-07-06
申请号：US839219
申请日：1997-04-22
申请人： Steven M. Eustis , Dale E. Pontius
发明人： Steven M. Eustis , Dale E. Pontius
CPC分类号： H03K5/15046
摘要： A pulse generator comprising a delay circuit uses a series of "n" delay stages to generate pulses that do not have distorted duty cycles. The output of the delay stage "n" feeds back to reset the delay stage "n-2". The output of each of the delay stages initially changes from a first logic state to a second logic stage at the leading edge of a pulse. The output of each delay stage switches back to the first logic state, or the trailing edge of the pulse, upon receipt of the feedback signal from a subsequent delay stage. The wave characteristics depend only on the rising edge of the pulse because the rising edge of the pulse of a future stage generates the falling edge of the current stage.
摘要翻译： 包括延迟电路的脉冲发生器使用一系列“n”个延迟级产生不具有失真占空比的脉冲。 延迟级“n”的输出反馈到复位延迟级“n-2”。 每个延迟级的输出在脉冲的前沿开始从第一逻辑状态改变到第二逻辑级。 当接收到来自后续延迟级的反馈信号时，每个延迟级的输出切换回到第一逻辑状态或脉冲的后沿。 波特性仅取决于脉冲的上升沿，因为未来级的脉冲的上升沿会产生当前级的下降沿。
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7.发明申请COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS 审中-公开可编程存储器结构和测试方法用于两个ASIC和基准测试环境公开(公告)号：US20080256405A1
公开(公告)日：2008-10-16
申请号：US12143007
申请日：2008-06-20
IPC分类号： G01R31/3185 , G06F11/25 , G01R31/3187
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/3202
摘要： A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip.
摘要翻译： 实现被配置为支持多个测试方法的可编译存储器结构的方法包括配置第一多个多路复用器，用于选择性地耦合至少一个数据输入路径和外部客户连接与与其相关联的对应内部存储器连接之间的至少一个地址路径。 第二多路复用器被配置为选择性地耦合功能存储器阵列连接和存储器逻辑连接之间的测试锁存器的输入，存储器逻辑连接耦合到至少一个数据输入路径，测试锁存器的输出定义数据 客户连接。 冲洗逻辑被配置为在与客户芯片相关联的逻辑的测试期间将数据从存储器逻辑连接引导到数据输出客户连接，以便于观察客户芯片上的存储器逻辑连接。
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公开(公告)号：US06928377B2
公开(公告)日：2005-08-09
申请号：US10658940
申请日：2003-09-09
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/1208
摘要： Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.
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公开(公告)号：US08239715B2
公开(公告)日：2012-08-07
申请号：US12144686
申请日：2008-06-24
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G11C7/02 , G11C7/04 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C29/1201 , G11C29/12015 , G11C29/48 , G11C2029/5602 , G11C2207/104
摘要： A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.
摘要翻译： 提供一种用于操作第一单元和提供其数据的第二单元之间的接口的方法。 该方法包括在LSSD_B和LSSD_C时钟之间的切换控制和系统时钟（CLK），以提供测试操作模式和功能操作模式，以根据单元运行的条件来优化建立和保持时间。 在测试模式下，数据由LSSD_C时钟启动。 在功能模式下，数据由系统时钟（CLK）发送到RAM。 还提供了一种方法来确定哪些存储器输入应该使用提供足够的建立和保持余量的电路。
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公开(公告)号：US20090319841A1
公开(公告)日：2009-12-24
申请号：US12144703
申请日：2008-06-24
IPC分类号： G06F11/267 , G01R31/28 , G01R31/317
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/48 , G11C2029/0401
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括耦合到数据处理单元输入的输入寄存器和测试操作模式和功能操作模式。 在测试模式操作中，寄存器以时钟模式操作，使得在测试操作模式期间，寄存器响应于时钟信号将数据传播到数据处理单元。 在功能操作模式中，寄存器以数据刷新模式运行，使得寄存器响应于该数据将数据传播到数据处理单元。 功能模式由刷新使能信号使能，测试模式通过刷新使能信号的相反状态使能。
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