公开(公告)号：US07043713B2

公开(公告)日：2006-05-09

申请号：US10640171

申请日：2003-08-12

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F17/50

CPC分类号： H03K19/17708 ,  H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

摘要翻译： 根据本发明，公开了一种用于定制一次性可配置集成电路以包括多时间可配置结构的方法。 这种方法包括，在一个实施例中，从用户接收电路功能的描述以在一次性可配置设备中实现，其中功能包括由用户指定为可重新配置的部分。 然后，根据本发明的实施例的方法对具有足够容量以容纳指定功能的可重构结构进行建模。 可选地，本发明的一些实施例增加了比实现指定功能所需的容量更多的容量以允许将来的重新编程。 该方法然后将可重构结构嵌入在一次性可配置设备中。 在某些实施例中，一次性可配置设备可以是掩模编程的MBA，门阵列或标准单元，而可重构结构是PLA或修改的PLA。

公开(公告)号：US06769109B2

公开(公告)日：2004-07-27

申请号：US09877170

申请日：2001-06-08

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F1750

CPC分类号： H03K19/17708 ,  H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

公开(公告)号：US06694491B1

公开(公告)日：2004-02-17

申请号：US09512783

申请日：2000-02-25

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F1750

CPC分类号： H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

摘要翻译： 根据本发明，公开了一种用于定制一次性可配置集成电路以包括多时间可配置结构的方法。 这种方法包括，在一个实施例中，从用户接收电路功能的描述以在一次性可配置设备中实现，其中功能包括由用户指定为可重新配置的部分。 然后，根据本发明的实施例的方法对具有足够容量以容纳指定功能的可重构结构进行建模。 可选地，本发明的一些实施例增加了比实现指定功能所需的容量更多的容量以允许将来的重新编程。 该方法然后将可重构结构嵌入在一次性可配置设备中。 在某些实施例中，一次性可配置设备可以是掩模编程的MBA，门阵列或标准单元，而可重构结构是PLA或修改的PLA。

公开(公告)号：US06399400B1

公开(公告)日：2002-06-04

申请号：US09272470

申请日：1999-03-19

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy

IPC分类号： H01L2166

CPC分类号： H01L22/20 ,  H01L22/34 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate array integrated circuit wafer is formed having M−N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M−N generic metal interconnection layers. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. In another embodiment, all M layers are deposited prior to performance and/or electrical testing; however, the Mth layer is not etched within the active die area prior to performance and/or electrical testing. Subsequent to binning based upon the test results, the final customization is performed by etching the Mth metal layer.

摘要翻译： 门阵列集成电路晶片形成为具有M-N个通用金属互连层，并且具有仅使用M-N通用金属互连层操作的性能和/或电测试电路。 性能和/或电气测试在通用制造完成之后，但在最终定制晶片之前进行。 基于性能和/或电气测试的结果，将晶片分类并分配给性能和/或产量箱。 在另一个实施例中，所有M层在性能和/或电气测试之前被沉积; 然而，在性能和/或电气测试之前，第M层不在有源管芯区域内被蚀刻。 在基于测试结果的合并之后，通过蚀刻第M个金属层来进行最终定制。

公开(公告)号：US6133582A

公开(公告)日：2000-10-17

申请号：US79016

申请日：1998-05-14

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy

IPC分类号： H01L21/66 ,  H01L27/118 ,  H01L23/58

CPC分类号： H01L22/20 ,  H01L27/11803 ,  H01L22/34 ,  H01L2924/0002

摘要： A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the active chip area and/or in the scribe line area between dies on the wafer. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. The contents of different bins are provided to different customers for addition of the final N application specific metal interconnection layers based upon the customer's performance and/or yield requirements. In another embodiment, all M layers are deposited prior to performance and/or electrical testing; however, the Mth layer is not etched within the active die area prior to performance and/or electrical testing. Subsequent to binning based upon the test results, the final customization is performed by etching the Mth metal layer. Further, a programmable gate array integrated circuit which has features for testing and binning for speed and performance grading prior to final personalization or programming on the top layer or layers of interconnecting material is provided.

摘要翻译： 门阵列集成电路晶片形成为具有M-N个通用金属互连层，并且具有仅使用M-N通用金属互连层操作的性能和/或电测试电路。 性能和电气测试电路位于晶片上的芯片的有源芯片区域和/或切割线区域中。 性能和/或电气测试在通用制造完成之后，但在最终定制晶片之前进行。 基于性能和/或电气测试的结果，将晶片分类并分配给性能和/或产量箱。 根据客户的性能和/或产量要求，将不同箱体的内容提供给不同的客户，以添加最终的N个特定应用的金属互连层。 在另一个实施例中，所有M层在性能和/或电气测试之前被沉积; 然而，在性能和/或电气测试之前，第M层不在有源管芯区域内被蚀刻。 在基于测试结果的合并之后，通过蚀刻第M个金属层来进行最终定制。 此外，提供了一种可编程门阵列集成电路，其具有用于在最终个性化或在互连材料的顶层或多层之间编程之前的速度和性能分级的测试和合并的特征。

公开(公告)号：US06770949B1

公开(公告)日：2004-08-03

申请号：US09144489

申请日：1998-08-31

申请人： Shafy Eltoukhy

发明人： Shafy Eltoukhy

IPC分类号： H01L2900

CPC分类号： H03L7/08

摘要： A system and method in accordance with the invention minimizes the redesign burden in tuning and/or customizing PLLs on ICs. Variable resistors are placed in the PLL in places that facilitate tuning. The variable resistors are formed with a set of at least three contacts, where each contact is in electrical communication with a resistive area. A metal layer is used to form leads to the resistive area, where each lead is formed to be in electrical communication with only a selected subset of contacts from the set. In one embodiment, only the uppermost metal layer used in forming the IC is used to form the leads. Because the uppermost metal layer is utilized, the resistor value can be adjusted simply by selecting the subsets of contacts that are to be in electrical communication with the uppermost metal layer. In this manner, only one metal layer needs to be adjusted in tuning and/or customizing a PLL, rather than having to redesign and re-layout all metal layers and vias in the IC.

摘要翻译： 根据本发明的系统和方法将调整和/或定制IC上的PLL的重新设计负担最小化。 可变电阻器放置在PLL中，便于调谐。 可变电阻器由一组至少三个触点形成，其中每个触点与电阻区域电连通。 金属层用于形成电阻区域的引线，其中每个引线形成为仅与来自该组的选定的触点子组电连通。 在一个实施例中，仅使用用于形成IC的最上层的金属层来形成引线。 因为利用最上层的金属层，所以可以简单地通过选择与最上层的金属层电连通的触点子集来调整电阻值。 以这种方式，在调谐和/或定制PLL期间只需要调整一个金属层，而不必重新设计和重新布置IC中的所有金属层和通孔。