公开(公告)号：US07849441B2

公开(公告)日：2010-12-07

申请号：US11426882

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

发明人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

IPC分类号： G06F9/44

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

摘要翻译： 提供了一种用于指定有状态的，面向事务的系统的方法。 该方法通过指定多个原始FlowModules来启动。 该方法包括在多个FlowModules中的每一个中定义至少一个FlowGate，其中每个FlowGate包括不可中断的过程代码序列，单个入口点，并由命名的并发调用进行调用。 从调用FlowGate指定一个Arc到被称为FlowGate的Arc，并且为被调用的FlowGate的每个命名调用生成一个Signal。 定义一个通道用于携带信号。 提供了用于在半导体器件中合成半导体器件和路由信号的方法。

公开(公告)号：US07320013B2

公开(公告)日：2008-01-15

申请号：US10726427

申请日：2003-12-02

申请人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

发明人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

IPC分类号： G06F5/01

CPC分类号： G06F5/01 ,  G06F7/49994

摘要： A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second operand has a greater bit width than the first operand. Next, the first operand is transformed by aligning a least significant bit of the first operand to a lowest bit position of a transformed operand having a bit size equal to the second operand. Then, the bits of the transformed operand are sign extended and padded in a manner to allow carry propagation. Next, the transformed operand is transmitted to the processor. A method for shifting operands and a processor are also provided.

摘要翻译： 提供了一种透明地呈现不同大小的待处理操作数的方法。 该方法通过提供具有第一位宽的第一操作数来启动。 然后，确定与处理器相关联的第二操作数的位宽度。 第二个操作数的位宽比第一个操作数大。 接下来，通过将第一操作数的最低有效位与具有等于第二操作数的位大小的变换操作数的最低位位置对齐来变换第一操作数。 然后，变换的操作数的位被符号扩展并以允许进位传播的方式填充。 接下来，将变换的操作数传送到处理器。 还提供了用于移位操作数和处理器的方法。

公开(公告)号：US07162630B2

公开(公告)日：2007-01-09

申请号：US10233303

申请日：2002-08-30

申请人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

发明人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

IPC分类号： H04L9/00 ,  H04L9/32

CPC分类号： H04L47/10 ,  H04L29/06 ,  H04L47/193 ,  H04L63/0272 ,  H04L63/0428 ,  H04L63/0485 ,  H04L63/061 ,  H04L63/08 ,  H04L63/164 ,  H04L67/06 ,  H04L67/28 ,  H04L67/2828 ,  H04L67/289 ,  H04L69/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163 ,  H04L69/166 ,  H04L69/22 ,  H04L69/24 ,  H04L69/329

摘要： An architecture for implementing host-based security such that data security may be applied whenever the confidential data leaves a host computer or a networked device. The improved method and architecture may be implemented in a single integrated circuit for speed, power consumption, and space-utilization reasons. Within the integrated circuit, a combination of hardware-implemented, network processor-implemented, and software-implemented functions may be provided. The innovative host-based security architecture may offer line-rate IPSec acceleration, TCP acceleration, or both.

摘要翻译： 用于实现基于主机的安全性的架构，使得每当机密数据离开主计算机或网络设备时可以应用数据安全性。 改进的方法和架构可以在单个集成电路中实现，用于速度，功率消耗和空间利用的原因。 在集成电路中，可以提供硬件实现的，网络处理器实现的和软件实现的功能的组合。 创新的基于主机的安全架构可以提供线速IPSec加速，TCP加速或两者兼容。

公开(公告)号：US06611932B2

公开(公告)日：2003-08-26

申请号：US10056686

申请日：2002-01-24

申请人： Dana How ,  Adi Srinivasan ,  Robert Osann, Jr. ,  Shridhar Mukund

发明人： Dana How ,  Adi Srinivasan ,  Robert Osann, Jr. ,  Shridhar Mukund

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.

摘要翻译： 公开了用于测试集成电路，特别是门阵列的系统，其在耦合阵列以形成用户设计的电路之前包括能够测试用户设计的电路的预先设计的逻辑。 预先设计的逻辑允许阵列中的逻辑块以“冻结”模式运行或在正常模式下运行，其中正常模式由用户设计的电路定义。 当逻辑块被选择为冻结时，逻辑块表现为一系列菊花链主主机触发器。 在正常模式下，逻辑块可以实现组合，顺序或其他功能，并且稍后将作为主从触发器。 此外，每个逻辑块进一步配置为可寻址模式控制，允许一旦激励数据被移位，孤立地选择逻辑块，简化测试生成并提高故障覆盖。

公开(公告)号：US07783035B2

公开(公告)日：2010-08-24

申请号：US11612438

申请日：2006-12-18

申请人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

发明人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

IPC分类号： H04L9/00 ,  G06F15/16

CPC分类号： F04D29/703 ,  F04D29/388

摘要： A network node is disclosed. The network node includes a host processor. The network node also includes an integrated circuit. The integrated circuit includes a hardware portion configured to perform a first set of TCP acceleration tasks that require a first speed level. The integrated circuit also includes a network protocol processor configured to perform a second set of TCP acceleration tasks that require a second speed level, which is lower than the first speed level. The integrated circuit further includes an embedded processor configured to perform a third set of TCP acceleration tasks that require a third speed level, which is lower than the second speed level. The network node further includes a plurality of data paths configured to couple the integrated circuit to the host processor, the plurality of data paths being implemented based on different protocols.

摘要翻译： 公开了一种网络节点。 网络节点包括主机处理器。 网络节点还包括集成电路。 集成电路包括被配置为执行需要第一速度级别的第一组TCP加速任务的硬件部分。 集成电路还包括被配置为执行第二组TCP加速任务的网络协议处理器，其需要低于第一速度级别的第二速度级别。 集成电路还包括被配置为执行需要低于第二速度级别的第三速度级别的第三组TCP加速任务的嵌入式处理器。 网络节点还包括被配置为将集成电路耦合到主处理器的多个数据路径，所述多个数据路径是基于不同协议来实现的。

公开(公告)号：US20100008155A1

公开(公告)日：2010-01-14

申请号：US12561460

申请日：2009-09-17

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G11C7/10 ,  G06F17/50 ,  H03K19/003 ,  H03K19/173

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括布置在多个列组中的多个存储器单元，每个列组具有用于独立多路可配置存取的多个列和多个外部位线。 列组在外部位线中具有第一，第二和第三层级。 层级的第一级提供与多个存储器单元的连接。 层级的第二级提供了用于将数据从列组中的每个列复用到中间位线的第一拼接器。 该层级的第三级包括用于将数据复用到从多个外部访问路径到中间位线的数据的第二拼接器。 还提供了一种结构可重构电路装置和用于设计电路的方法。

公开(公告)号：US07614020B2

公开(公告)日：2009-11-03

申请号：US11426880

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括布置在多个列组中的多个存储器单元，每个列组具有用于独立多路可配置存取的多个列和多个外部位线。 列组在外部位线中具有第一，第二和第三层级。 层级的第一级提供与多个存储器单元的连接。 层级的第二级提供了用于将数据从列组中的每个列复用到中间位线的第一拼接器。 该层级的第三级包括用于将数据复用到从多个外部访问路径到中间位线的数据的第二拼接器。 还提供了一种结构可重构电路装置和用于设计电路的方法。

公开(公告)号：US20070150854A1

公开(公告)日：2007-06-28

申请号：US11426882

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

发明人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

IPC分类号： G06F9/44

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

摘要翻译： 提供了一种用于指定有状态的，面向事务的系统的方法。 该方法通过指定多个原始FlowModules来启动。 该方法包括在多个FlowModules的每一个内定义至少一个FlowGate，其中每个FlowGate包括不可中断的过程代码序列，单个入口点，并由命名的并发调用进行调用。 从调用FlowGate指定一个Arc到被称为FlowGate的Arc，并且为被调用的FlowGate的每个命名调用生成一个Signal。 定义一个通道用于携带信号。 提供了用于在半导体器件中合成半导体器件和路由信号的方法。

公开(公告)号：US07043713B2

公开(公告)日：2006-05-09

申请号：US10640171

申请日：2003-08-12

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F17/50

CPC分类号： H03K19/17708 ,  H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

摘要翻译： 根据本发明，公开了一种用于定制一次性可配置集成电路以包括多时间可配置结构的方法。 这种方法包括，在一个实施例中，从用户接收电路功能的描述以在一次性可配置设备中实现，其中功能包括由用户指定为可重新配置的部分。 然后，根据本发明的实施例的方法对具有足够容量以容纳指定功能的可重构结构进行建模。 可选地，本发明的一些实施例增加了比实现指定功能所需的容量更多的容量以允许将来的重新编程。 该方法然后将可重构结构嵌入在一次性可配置设备中。 在某些实施例中，一次性可配置设备可以是掩模编程的MBA，门阵列或标准单元，而可重构结构是PLA或修改的PLA。

公开(公告)号：US06961893B1

公开(公告)日：2005-11-01

申请号：US10113147

申请日：2002-03-28

申请人： Shridhar Mukund ,  Manish Mahajan ,  Vasantha Srirambhatla ,  T.V.P. Kameswar Rao ,  Anjan Mitra

发明人： Shridhar Mukund ,  Manish Mahajan ,  Vasantha Srirambhatla ,  T.V.P. Kameswar Rao ,  Anjan Mitra

IPC分类号： H03M13/09 ,  H03M13/11 ,  H04L1/00 ,  H04L29/06 ,  H03M13/00

CPC分类号： H03M13/091

摘要： A method and apparatus for performing a cyclic redundancy check (CRC) process is provided. The CRC is capable of being performed on data received out of order without having to store and assemble the data. One exemplary method for computing a CRC for a transmitted data stream initiates with performing a CRC process on a first segment of the data stream to generate a first CRC remainder. Next, the first CRC remainder for the first segment is projected. Then, the CRC process on a second segment of the data stream is performed to generate a second CRC remainder. Next, the second CRC remainder for the second segment is projected. Then, the projected remainders are combined to calculate a complete CRC remainder for the data stream in an order independent fashion. Data streams including multiple segments can be handled by the CRC process.

摘要翻译： 提供了一种用于执行循环冗余校验（CRC）处理的方法和装置。 CRC能够对不依次接收的数据执行，而不必存储和组合数据。 用于计算发送数据流的CRC的一个示例性方法通过在数据流的第一段上执行CRC处理来产生第一CRC余数。 接下来，投影第一段的第一个CRC余数。 然后，执行数据流的第二段上的CRC处理以产生第二CRC余数。 接下来，投影第二段的第二CRC余数。 然后，将投影的余数组合起来，以独立的顺序为数据流计算完整的CRC余数。 包括多个段的数据流可以由CRC处理来处理。