公开(公告)号：US07043713B2

公开(公告)日：2006-05-09

申请号：US10640171

申请日：2003-08-12

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F17/50

CPC分类号： H03K19/17708 ,  H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

摘要翻译： 根据本发明，公开了一种用于定制一次性可配置集成电路以包括多时间可配置结构的方法。 这种方法包括，在一个实施例中，从用户接收电路功能的描述以在一次性可配置设备中实现，其中功能包括由用户指定为可重新配置的部分。 然后，根据本发明的实施例的方法对具有足够容量以容纳指定功能的可重构结构进行建模。 可选地，本发明的一些实施例增加了比实现指定功能所需的容量更多的容量以允许将来的重新编程。 该方法然后将可重构结构嵌入在一次性可配置设备中。 在某些实施例中，一次性可配置设备可以是掩模编程的MBA，门阵列或标准单元，而可重构结构是PLA或修改的PLA。

公开(公告)号：US06769109B2

公开(公告)日：2004-07-27

申请号：US09877170

申请日：2001-06-08

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F1750

CPC分类号： H03K19/17708 ,  H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

公开(公告)号：US06694491B1

公开(公告)日：2004-02-17

申请号：US09512783

申请日：2000-02-25

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F1750

CPC分类号： H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

摘要翻译： 根据本发明，公开了一种用于定制一次性可配置集成电路以包括多时间可配置结构的方法。 这种方法包括，在一个实施例中，从用户接收电路功能的描述以在一次性可配置设备中实现，其中功能包括由用户指定为可重新配置的部分。 然后，根据本发明的实施例的方法对具有足够容量以容纳指定功能的可重构结构进行建模。 可选地，本发明的一些实施例增加了比实现指定功能所需的容量更多的容量以允许将来的重新编程。 该方法然后将可重构结构嵌入在一次性可配置设备中。 在某些实施例中，一次性可配置设备可以是掩模编程的MBA，门阵列或标准单元，而可重构结构是PLA或修改的PLA。

公开(公告)号：US06399400B1

公开(公告)日：2002-06-04

申请号：US09272470

申请日：1999-03-19

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy

IPC分类号： H01L2166

CPC分类号： H01L22/20 ,  H01L22/34 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate array integrated circuit wafer is formed having M−N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M−N generic metal interconnection layers. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. In another embodiment, all M layers are deposited prior to performance and/or electrical testing; however, the Mth layer is not etched within the active die area prior to performance and/or electrical testing. Subsequent to binning based upon the test results, the final customization is performed by etching the Mth metal layer.

摘要翻译： 门阵列集成电路晶片形成为具有M-N个通用金属互连层，并且具有仅使用M-N通用金属互连层操作的性能和/或电测试电路。 性能和/或电气测试在通用制造完成之后，但在最终定制晶片之前进行。 基于性能和/或电气测试的结果，将晶片分类并分配给性能和/或产量箱。 在另一个实施例中，所有M层在性能和/或电气测试之前被沉积; 然而，在性能和/或电气测试之前，第M层不在有源管芯区域内被蚀刻。 在基于测试结果的合并之后，通过蚀刻第M个金属层来进行最终定制。

公开(公告)号：US6133582A

公开(公告)日：2000-10-17

申请号：US79016

申请日：1998-05-14

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy

IPC分类号： H01L21/66 ,  H01L27/118 ,  H01L23/58

CPC分类号： H01L22/20 ,  H01L27/11803 ,  H01L22/34 ,  H01L2924/0002

摘要： A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the active chip area and/or in the scribe line area between dies on the wafer. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. The contents of different bins are provided to different customers for addition of the final N application specific metal interconnection layers based upon the customer's performance and/or yield requirements. In another embodiment, all M layers are deposited prior to performance and/or electrical testing; however, the Mth layer is not etched within the active die area prior to performance and/or electrical testing. Subsequent to binning based upon the test results, the final customization is performed by etching the Mth metal layer. Further, a programmable gate array integrated circuit which has features for testing and binning for speed and performance grading prior to final personalization or programming on the top layer or layers of interconnecting material is provided.

摘要翻译： 门阵列集成电路晶片形成为具有M-N个通用金属互连层，并且具有仅使用M-N通用金属互连层操作的性能和/或电测试电路。 性能和电气测试电路位于晶片上的芯片的有源芯片区域和/或切割线区域中。 性能和/或电气测试在通用制造完成之后，但在最终定制晶片之前进行。 基于性能和/或电气测试的结果，将晶片分类并分配给性能和/或产量箱。 根据客户的性能和/或产量要求，将不同箱体的内容提供给不同的客户，以添加最终的N个特定应用的金属互连层。 在另一个实施例中，所有M层在性能和/或电气测试之前被沉积; 然而，在性能和/或电气测试之前，第M层不在有源管芯区域内被蚀刻。 在基于测试结果的合并之后，通过蚀刻第M个金属层来进行最终定制。 此外，提供了一种可编程门阵列集成电路，其具有用于在最终个性化或在互连材料的顶层或多层之间编程之前的速度和性能分级的测试和合并的特征。

公开(公告)号：US09529920B2

公开(公告)日：2016-12-27

申请号：US14820433

申请日：2015-08-06

申请人： Robert Osann, Jr.

发明人： Robert Osann, Jr.

IPC分类号： G06F17/30

CPC分类号： G06F17/30867 ,  G06F17/30554 ,  G06F17/30696 ,  G06F17/30905 ,  G06F17/30991

摘要： A system and method for automatically analyzing and characterizing Internet search results and annotating a search results page according to specific characteristics of each webpage located at a URL corresponding to a search result. Such characteristics include the composition of each search results webpage as well as which search term elements are present in a webpage located at a URL corresponding to a search result out of those search term elements that were submitted to a search engine to produce the search results webpage. Further, search results are annotated to indicate which search term elements are present in a descendent webpage of a webpage located at a URL corresponding to a search result. Search results may also be optionally filtered according to specific characteristics of a webpage located at a search results URL such that certain categories of webpage are excluded from being referenced in the displayed search results.

公开(公告)号：US09386141B2

公开(公告)日：2016-07-05

申请号：US14791423

申请日：2015-07-04

申请人： Robert Osann, Jr.

发明人： Robert Osann, Jr.

IPC分类号： H04W4/22 ,  H04M1/725 ,  H04W76/00 ,  H04W4/02

CPC分类号： H04M1/72538 ,  H04W4/025 ,  H04W4/029 ,  H04W4/90 ,  H04W76/50

摘要： Systems and methods are disclosed for tracking the progress of a trip where a person or persons wish to have a third party automatically informed of a delayed return. For long duration trips and/or trips to distant destinations, people typically make provision for having their pets and/or children watched over. However for short trips, they typically do not, especially with respect to their pets. The disclosed methods provide monitoring of a trip's progress such that if a traveler doesn't return home by a certain time, a third party is notified, thus avoiding a prolonged period of time wherein the pets and/or children are unattended, especially in the event of a catastrophic accident. The third party may be notified if an arrival time is predicted to be delayed, and when an actual arrival occurs. Provision is also included for adjusting the trip duration to delay or advance a designated arrival time.

摘要翻译： 公开了系统和方法，用于跟踪旅行的进展情况，其中希望让第三者自动通知延迟返回。 长途旅行和/或到远方目的地的旅行，人们通常会让他们的宠物和/或儿童观看。 然而，对于短途旅行，他们通常不会，特别是对于他们的宠物。 所公开的方法提供对旅行进度的监视，使得如果旅行者不在一定时间内回家，则通知第三方，从而避免长时间的时间，其中宠物和/或儿童是无人值守的，特别是在 发生灾难性事故。 如果预计到达时间延迟，并且实际到达时，可以通知第三方。 还包括用于调整行程持续时间以延迟或提前指定到达时间的规定。

公开(公告)号：US08122475B2

公开(公告)日：2012-02-21

申请号：US12069877

申请日：2008-02-12

申请人： Robert Osann, Jr. ,  Joseph A. Zott ,  Samuel W. Beal

发明人： Robert Osann, Jr. ,  Joseph A. Zott ,  Samuel W. Beal

IPC分类号： H04N7/173

CPC分类号： H04N21/4782 ,  H04N21/4122 ,  H04N21/422 ,  H04N21/42204 ,  H04N21/4227 ,  H04N21/43615 ,  H04N21/4438 ,  H04N21/47202 ,  H04N21/4828

摘要： Systems and methods are described for remote control of a media server computer from a controller device, typically a laptop computer, where remote operation of the media server, including the selection of videos and other digital media may be performed from the controller while normal TV programming (cable, satellite, or broadcast) is viewed on the TV. Other embodiments describe background operations performed on the controller device, the media server, or both, such that new videos may be located on the web or locally on the LAN while a current video is playing on the media server and viewed on the TV. Methods are also described for more reliably establishing network connections between the controller and media server, and systems and methods are described for implementing a multi-video display on the media server where videos to be displayed on the media server are displayed on and selected by a controller device.

摘要翻译： 描述了用于从控制器设备（通常为笔记本电脑）远程控制媒体服务器计算机的系统和方法，其中媒体服务器的远程操作包括视频和其他数字媒体的选择可以从控制器执行，而正常的电视节目 （有线，卫星或广播）在电视机上观看。 其他实施例描述了在控制器设备，媒体服务器或两者上执行的后台操作，使得当视频正在媒体服务器上播放并且在电视机上观看时，新的视频可能位于网络上或本地LAN上。 还描述了用于更可靠地建立控制器和媒体服务器之间的网络连接的方法，并且描述了系统和方法，用于在媒体服务器上实现要在媒体服务器上显示的视频被显示在媒体服务器上并由其选择的媒体服务器上的多视频显示 控制器设备。

公开(公告)号：US07241635B1

公开(公告)日：2007-07-10

申请号：US10704850

申请日：2003-11-10

申请人： Robert Osann, Jr.

发明人： Robert Osann, Jr.

IPC分类号： H01L21/44

CPC分类号： H01L22/14 ,  H01L22/20

摘要： A binning method is disclosed for measuring semiconductor devices for certain parameters and placing specific devices into different categories or “bins” according to the measured parameters. Measurable parameters include performance/speed-grading, power consumption, current leakage, and the ability to operate at certain temperature extremes. A method for speed grading semi-custom ASIC devices is specifically described that does not require removing partially completed wafers from the fab line for testing. To speed-grade a new boat of partially completed un-customized wafers, a small number of wafers (1 or 2) are processed to completion while being customized specifically for a customer design requiring only the slowest bin. These wafer(s) are then performance tested and the remaining wafers in the boat are certified according to these results for their performance level and placed in a wafer bank for later use.

摘要翻译： 公开了一种用于测量某些参数的半导体器件并根据所测量的参数将特定器件置于不同类别或“垃圾桶”中的合并方法。 可测量的参数包括性能/速度分级，功耗，电流泄漏以及在某些极端温度下工作的能力。 具体描述了一种用于速度分级的半定制ASIC器件的方法，其不需要从用于测试的制造线生产线中去除部分完成的晶片。 为了对新的部分完成的未定制晶片进行分级，少量晶圆（1或2）被完成处理，同时专门针对仅需要最慢箱的客户设计进行定制。 然后对这些晶片进行性能测试，并根据这些结果验证船上的剩余晶片的性能水平，并将其放置在晶片库中供以后使用。

公开(公告)号：US07062744B2

公开(公告)日：2006-06-13

申请号：US10655060

申请日：2003-09-03

申请人： Robert Osann, Jr.

发明人： Robert Osann, Jr.

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F15/7867 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3885 ,  G06F9/3897 ,  G06F17/5054

摘要： To serve prototype and initial production requirements, an emulation solution is described where an ASIC semiconductor device die containing primarily fixed functions, for example a DSP processor with programmable instruction interface, is mounted in the same package as a conventional FPGA device—the FPGA in this example implementing custom instructions for DSP algorithm acceleration and connecting primarily to the fixed function device. A fully integrated, single die ASIC solution is then available for migration of designs to higher volume production where some of the field programmable function will be replaced with fixed function. The base wafer for the ASIC device used in the prototype package and base wafer for the volume production ASIC device may be the same.

摘要翻译： 为了提供原型和初始生产要求，描述了一种仿真解决方案，其中主要固定功能的ASIC半导体器件管芯（例如具有可编程指令接口的DSP处理器）安装在与常规FPGA器件相同的封装中 - 此处的FPGA 实现DSP算法加速的自定义指令并主要连接到固定功能设备的示例。 然后，完全集成的单芯片ASIC解决方案可用于将设计迁移到更大批量的生产，其中一些现场可编程功能将被固定功能替代。 用于批量生产ASIC器件的原型封装和基底晶片中的用于ASIC器件的基底晶片可以是相同的。