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    Configurable real prototype hardware using cores and memory macros
    1.
    发明授权
    Configurable real prototype hardware using cores and memory macros 失效
    可配置的真实原型硬件使用内核和内存宏

    公开(公告)号：US06978234B1

    公开(公告)日：2005-12-20

    申请号：US09602369

    申请日：2000-06-23

    申请人： Robert P. Battaline ,  Emory D. Keller ,  Sebastian T. Ventrone

    发明人： Robert P. Battaline ,  Emory D. Keller ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22 ,  G06F11/26 ,  G06F13/00

    CPC分类号： G06F11/261

    摘要： A method of creating a prototype data processing system, by configuring a hardware development chip (HDC) according to user-defined settings, building user-defined logic adapted to function with the configured development chip, and allowing for the re-configuration of the HDC and user-defined logic after debugging. The HDC has several data processing macros including a processor core macro, a ROM emulation macro, a memory macro, and a bus macro. The macros may be configured by a configuration pin block which is connected to external configuration pins on the HDC. Customer logic is built using a field programmable gate array, which is interconnected with external ports of the HDC. The HDC and customer logic are verified using a debug port on the HDC, which is connected to a debug workstation. The invention allows a user to easily and quickly debug an application-specific integrated circuit (ASIC) design with a unique version of selected processor cores.

    摘要翻译： 一种创建原型数据处理系统的方法，通过根据用户定义的设置配置硬件开发芯片（HDC），构建适用于配置的开发芯片的用户定义逻辑，并允许重新配置HDC 和调试后的用户定义逻辑。 HDC具有多个数据处理宏，包括处理器核心宏，ROM仿真宏，存储器宏和总线宏。 宏可以由连接到HDC上的外部配置引脚的配置引脚块来配置。 客户逻辑使用与HDC的外部端口互连的现场可编程门阵列构建。 HDC和客户逻辑使用HDC上的调试端口进行验证，该调试端口连接到调试工作站。 本发明允许用户使用所选择的处理器核心的唯一版本容易且快速地调试专用集成电路（ASIC）设计。

    Performance monitoring through JTAG 1149.1 interface
    2.
    发明授权
    Performance monitoring through JTAG 1149.1 interface 失效
    通过JTAG 1149.1接口进行性能监控

    公开(公告)号：US5768152A

    公开(公告)日：1998-06-16

    申请号：US705871

    申请日：1996-08-28

    申请人： Robert P. Battaline ,  James R. Robinson ,  Edward H. Welbon ,  Ralph J. Williams

    发明人： Robert P. Battaline ,  James R. Robinson ,  Edward H. Welbon ,  Ralph J. Williams

    IPC分类号： G01R31/3185 ,  G06F11/34 ,  G01B17/00

    CPC分类号： G06F11/348 ,  G01R31/318533 ,  G06F11/3409 ,  G06F2201/86 ,  G06F2201/88

    摘要： Disclosed is a system and method of providing performance analysis on integrated circuit devices and systems using an IEEE JTAG 1149.1 interface. An integrated circuit device is described that includes an execution control register for receiving a control code from an external device via the JTAG interface, a means for selecting and coupling to one or more specific logic circuits on the device, one or more counters for recording specific events occurring on the logic circuits, and a counter register for managing the counter data and outputting it via the JTAG interface.

    摘要翻译： 公开了一种使用IEEE JTAG 1149.1接口在集成电路设备和系统上提供性能分析的系统和方法。 描述了一种集成电路装置，其包括用于经由JTAG接口从外部设备接收控制代码的执行控制寄存器，用于选择和耦合到设备上的一个或多个特定逻辑电路的装置，一个或多个用于记录特定 在逻辑电路上发生的事件，以及用于管理计数器数据并经由JTAG接口输出的计数器寄存器。