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13 条记录 (耗时 0.02 秒)

    Time stamp offset in data packet bundling
    1.
    发明授权
    Time stamp offset in data packet bundling 有权
    数据包捆绑中的时间戳偏移

    公开(公告)号：US08228956B2

    公开(公告)日：2012-07-24

    申请号：US11315544

    申请日：2005-12-22

    申请人： Robert S. Gammenthaler, Jr. ,  Brian Tatum

    发明人： Robert S. Gammenthaler, Jr. ,  Brian Tatum

    IPC分类号： H04J3/06

    CPC分类号： H04L43/12 ,  H04L43/00 ,  H04L43/04 ,  H04L43/106

    摘要： A system, method, and computer readable medium for time stamp offset in data packet bundling including filling a globally distributed time stamp based upon a globally distributed time, receiving a signal unit, resolving a difference in time between the globally distributed time stamp and the reception of the signal unit and assigning a time offset based upon the resolved time difference.

    摘要翻译： 一种用于数据分组捆绑中的时间戳偏移的系统，方法和计算机可读介质，包括基于全局分布的时间填充全局分布的时间戳，接收信号单元，解决全球分布的时间戳和接收之间的时间差 并且基于分辨的时间差来分配时间偏移。

    Context controlled data tap utilizing parallel logic for integrated link monitoring
    2.
    发明授权
    Context controlled data tap utilizing parallel logic for integrated link monitoring 有权
    上下文控制数据挖掘利用并行逻辑进行集成链路监控

    公开(公告)号：US08565095B2

    公开(公告)日：2013-10-22

    申请号：US11315512

    申请日：2005-12-22

    申请人： Robert S. Gammenthaler, Jr. ,  Jace Files

    发明人： Robert S. Gammenthaler, Jr. ,  Jace Files

    IPC分类号： H04J3/14

    CPC分类号： H04L43/00 ,  H04L43/106

    摘要： A system, method, and computer readable medium for context controlled data tapping utilizing parallel logic for integrated link monitoring including receiving a signal unit, indexing to a state associated with a current channel to determine a current context of the signal unit in parallel to host processing and assigning a bundle overhead associated with the signal unit.

    摘要翻译： 一种用于利用用于集成链路监视的并行逻辑的上下文控制数据分接的系统，方法和计算机可读介质，包括接收信号单元，索引到与当前信道相关联的状态，以与主机处理并行地确定信号单元的当前上下文 以及分配与所述信号单元相关联的束开销。

    Memory card and system for updating distributed memory
    3.
    发明授权
    Memory card and system for updating distributed memory 有权
    用于更新分布式存储器的存储卡和系统

    公开(公告)号：US06865637B1

    公开(公告)日：2005-03-08

    申请号：US09891999

    申请日：2001-06-26

    申请人： Ignacio A. Linares ,  Robert S. Gammenthaler, Jr. ,  Edwin J. Burger

    发明人： Ignacio A. Linares ,  Robert S. Gammenthaler, Jr. ,  Edwin J. Burger

    IPC分类号： G06F1/00 ,  H04L12/66 ,  H04Q3/00

    CPC分类号： H04L12/66

    摘要： A memory card cooperating with a network interface for receiving data entry and update signals from a database manager via a switch fabric and with a bus interface for outputting data on a system bus disposed in a system shelf, which shelf forms at least a portion of a telecommunications node having a distributed scalable database system. The memory card is operable to contain at least a portion of the distributed database in a high speed, high density memory block disposed thereon, which memory block is coupled to a network interface controller via a first memory interface and to a bus interface controller via a second memory interface. An arbiter is coupled to the first and second memory interfaces for arbitrating data input operations and data output operations with respect to the memory block.

    摘要翻译： 与网络接口协作的存储卡，用于经由交换结构从数据库管理器接收数据输入和更新信号，并且具有用于在布置在系统架中的系统总线上输出数据的总线接口，所述系统总线架构形成至少一部分 电信节点具有分布式可扩展数据库系统。 存储卡可操作以将分布式数据库的至少一部分包含在其上设置的高速，高密度存储器块中，该存储块经由第一存储器接口耦合到网络接口控制器，并经由 第二存储器接口。 仲裁器耦合到第一和第二存储器接口，用于对相对于存储器块的数据输入操作和数据输出操作进行仲裁。

    Switch architecture using multiple crossbars
    5.
    发明授权
    Switch architecture using multiple crossbars 有权
    使用多个交叉开关的交换架构

    公开(公告)号：US07197032B1

    公开(公告)日：2007-03-27

    申请号：US09927190

    申请日：2001-08-10

    申请人： Robert S. Gammenthaler, Jr. ,  Ignacio A. Linares ,  James C. McKinley ,  Teck Q. Chin ,  Gerald R. Dubois

    发明人： Robert S. Gammenthaler, Jr. ,  Ignacio A. Linares ,  James C. McKinley ,  Teck Q. Chin ,  Gerald R. Dubois

    IPC分类号： H04L12/50

    CPC分类号： H04L49/15 ,  H04L49/101 ,  H04L49/30

    摘要： The present invention provides an apparatus, system and method of increasing port availability for a communication switch. First, second and third M port crossbars are arranged to provide a crossbar with a increased number of ports available for the communication switch. K ports of a first M port crossbar are individually coupled to K ports of a second and a third M port crossbar via interconnect buses. Further, K ports of the second and third M port crossbars are individually coupled via interconnect buses resulting in L available ports on each the M port crossbars in which M>L>K.

    摘要翻译： 本发明提供了一种提高通信交换机的端口可用性的装置，系统和方法。 首先，第二和第三M端口十字条布置成为交叉开关提供可用于通信开关的更多端口。 第一M端口横杆的K个端口通过互连总线分别耦合到第二和第三M端口交叉开关的K个端口。 此外，第二和第三M端口交叉开关的K个端口通过互连总线单独耦合，从而在M> L> K的每个M端口交叉开关上产生L个可用端口。

    Method and apparatus for controlling signaling links in a telecommunications system
    6.
    发明授权
    Method and apparatus for controlling signaling links in a telecommunications system 失效
    用于控制电信系统中的信令链路的方法和装置

    公开(公告)号：US06768735B1

    公开(公告)日：2004-07-27

    申请号：US09541123

    申请日：2000-03-31

    申请人： Robert S. Gammenthaler, Jr. ,  Serge F. Fourcand ,  David W. Wynn

    发明人： Robert S. Gammenthaler, Jr. ,  Serge F. Fourcand ,  David W. Wynn

    IPC分类号： H04Q1100

    CPC分类号： H04Q3/0025

    摘要： In particular embodiments, the present invention provides an apparatus for controlling a signaling link. The apparatus includes a plurality of receivers and a plurality of drivers. Each receiver receives signaling messages from one of a plurality of first signaling links, and each driver sends signaling messages over one of a plurality of second signaling links. The apparatus also includes an interface that receives signaling messages and control data from a control module and sends signaling messages and control data to the control module. The apparatus further includes a processor coupled to the receivers, the drivers, and the interface. The processor receives signaling messages from the receivers and multiplexes portions of the signaling messages together for communication through the interface. The processor also receives portions of signaling messages from the interface and demultiplexes the portions for communication to the drivers.

    摘要翻译： 在具体实施例中，本发明提供了一种用于控制信令链路的装置。 该装置包括多个接收器和多个驱动器。 每个接收器从多个第一信令链路之一接收信令消息，并且每个驱动器通过多个第二信令链路之一发送信令消息。 该装置还包括从控制模块接收信令消息和控制数据并向控制模块发送信令消息和控制数据的接口。 该装置还包括耦合到接收器，驱动器和接口的处理器。 处理器从接收器接收信令消息，并将信令消息的一部分复用在一起以通过接口进行通信。 处理器还从接口接收信令消息的部分，并将该部分解复用于与驱动程序的通信。

    DSO timing source transient compensation
    9.
    发明授权
    DSO timing source transient compensation 有权
    DSO定时源瞬态补偿

    公开(公告)号：US07209492B2

    公开(公告)日：2007-04-24

    申请号：US10122461

    申请日：2002-04-15

    申请人： Matthew J. Marcoux ,  Robert S. Gammenthaler, Jr.

    发明人： Matthew J. Marcoux ,  Robert S. Gammenthaler, Jr.

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0688 ,  G06F1/10

    摘要： System and method for compensating for DS0 timing source transients, such as may occur during a switchover to a new external reference, is described. In one embodiment, an SFI control signal is monitored for embedded frame position information. When the frame position information is initially detected, a 10-bit frame clock counter is reset to zero. The counter is then incremented using an 8.192 MHz clock. From that point on, each time the SFI frame position information is detected, the value of the frame clock counter is checked. If the counter value is zero, the counter continues to run freely. If the counter value is non-zero and the most significant bit (“MSB”) thereof is zero, the count of the frame clock counter is held for one clock period. If the counter value is non-zero and the MSB thereof is one, the count of the frame clock counter is advanced by a value of two, rather than one, for one clock period.

    摘要翻译： 描述了用于补偿DS0定时源瞬变的系统和方法，例如在切换到新的外部参考时可能发生的系统和方法。 在一个实施例中，对嵌入的帧位置信息监视SFI控制信号。 当最初检测到帧位置信息时，10位帧时钟计数器被复位为零。 然后使用8.192MHz时钟递增计数器。 从那时开始，每当检测到SFI帧位置信息时，检查帧时钟计数器的值。 如果计数器值为零，则计数器继续自由运行。 如果计数器值不为零并且其最高有效位（“MSB”）为零，则帧时钟计数器的计数保持一个时钟周期。 如果计数器值不为零并且其MSB为1，则在一个时钟周期内帧时钟计数器的计数提前两个值而不是一个。

    State machine architecture partitionable into control and data planes
    10.
    发明授权
    State machine architecture partitionable into control and data planes 有权
    状态机架构可分割成控制和数据平面

    公开(公告)号：US06985968B1

    公开(公告)日：2006-01-10

    申请号：US09853387

    申请日：2001-05-11

    申请人： Robert S. Gammenthaler, Jr.

    发明人： Robert S. Gammenthaler, Jr.

    IPC分类号： G06F15/16

    CPC分类号： H04Q3/0025 ,  H04Q2213/13056 ,  H04Q2213/13176 ,  H04Q2213/13204

    摘要： A system and method for optimizing state machine transitional performance in a high speed link (HSL) protocol stack at an application node disposed in a network. An input event decoder and a state decoder decode an input event and state-specific context information relating to a particular protocol layer involved in a layer service for a specific connection. The decoded state-specific context information is utilized for personalizing a generic state machine (GSM) logic structure in order to effectuate a layer-specific state logic package that is partitionable into a control plane and a data plane. The decoded input event is processed by the personalized state machine to generate encodable output event and next-state information. In parallel with the control plane operations, parametric tests and data operations with respect to the layer service are performed in the data plane, thereby improving state machine transitional processing in the application node.

    摘要翻译： 一种用于在布置在网络中的应用节点处优化高速链路（HSL）协议栈中的状态机过渡性能的系统和方法。 输入事件解码器和状态解码器对涉及特定连接的层服务中涉及的特定协议层的输入事件和状态特定上下文信息进行解码。 解码的状态特定上下文信息用于个性化通用状态机（GSM）逻辑结构，以便实现可分割成控制平面和数据平面的层特定状态逻辑包。 解码的输入事件由个性化状态机处理以产生可编码的输出事件和下一状态信息。 与控制平面操作并行，在数据平面中执行相对于层服务的参数测试和数据操作，从而改善应用节点中的状态机过渡处理。