公开(公告)号：US06662360B1

公开(公告)日：2003-12-09

申请号：US09407105

申请日：1999-09-27

申请人： Robert William Hay ,  James Allan Kahle ,  Brian R. Konigsburg ,  David Stephen Levitan ,  Balaram Sinharoy

发明人： Robert William Hay ,  James Allan Kahle ,  Brian R. Konigsburg ,  David Stephen Levitan ,  Balaram Sinharoy

IPC分类号： G06F944

CPC分类号： G06F9/3846 ,  G06F9/3848

摘要： A method and system is disclosed for software manipulation of hardware prediction mechanism in a data processor with software prediction. The hardware branch prediction mechanism is enhanced with at least two bits for path prediction. These bits are settable by a software and are capable of overriding the hardware branch prediction mechanism. Branch prediction information is encoded into a branch instruction in the software. This information includes a pre-determined value for each bit. Finally, a branch path of said instruction is predicted based on the value of the bits.

摘要翻译： 公开了一种用于软件预测的数据处理器中硬件预测机制的软件操纵的方法和系统。 用于路径预测的至少两个比特来增强硬件分支预测机制。 这些位可由软件设置，并能够覆盖硬件分支预测机制。 分支预测信息被编码成软件中的分支指令。 该信息包括每个位的预定值。 最后，基于比特的值来预测所述指令的分支路径。

公开(公告)号：US06848044B2

公开(公告)日：2005-01-25

申请号：US09801608

申请日：2001-03-08

申请人： Lee Evan Eisen ,  James Allan Kahle ,  Balaram Sinharoy ,  William John Starke

发明人： Lee Evan Eisen ,  James Allan Kahle ,  Balaram Sinharoy ,  William John Starke

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3861

摘要： A method of performing operations to a link stack including the step of performing a Pop operation from the link stack which includes the substeps of storing a first pointer value to the link stack, the first pointer value being the value of a pointer to the link stack before the Pop operation, and storing a first address including a first tag popped from the link stack. The method further includes the step of performing a Push operation to the link stack which includes the substeps of storing a second address including a second tag being Pushed into the link stack and storing a second pointer to the link stack, the second pointer being the value of the pointer to the link stack after the Push operation. The method additionally provides for the recovering of the link stack following an instruction flush which includes the substeps of comparing the first pointer value and the second value, comparing the first tag and the second tag, and replacing an address at the top of the link stack with the first address when the first and second pointers match and the first and second tags match.

摘要翻译： 一种对链接堆栈执行操作的方法，包括从链路堆栈执行弹出操作的步骤，该链路栈包括将第一指针值存储到链路栈的子步骤，第一指针值是指向链路栈的指针的值 并且存储包括从链接堆栈弹出的第一标签的第一地址。 该方法还包括对链路堆栈执行Push操作的步骤，该链路栈包括存储第二地址的子步骤，该第二地址包括被推入到链路栈中的第二标签，并将第二指针存储到链路栈，第二指针是值 在Push操作后指向链接堆栈的指针。 该方法另外提供了在包括比较第一指针值和第二值的子步骤的指令刷新之后恢复链路栈，比较第一标签和第二标签，以及替换链路栈顶部的地址 当第一和第二指针匹配并且第一和第二标签匹配时具有第一地址。

公开(公告)号：US07120784B2

公开(公告)日：2006-10-10

申请号：US10425064

申请日：2003-04-28

申请人： Gregory William Alexander ,  Scott Bruce Frommer ,  David Stephen Levitan ,  Balaram Sinharoy

发明人： Gregory William Alexander ,  Scott Bruce Frommer ,  David Stephen Levitan ,  Balaram Sinharoy

IPC分类号： G06F9/40 ,  G06F9/00

CPC分类号： G06F9/3806 ,  G06F9/30189 ,  G06F9/3844 ,  G06F9/3851

摘要： Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.

摘要翻译： 分支预测逻辑被增强以提供用于某些条件的监视功能，其指示使用单独的BHT和预测的目标地址高速缓存将为分支预测提供更好的结果。 分支预测逻辑通过逻辑分割BHT和计数高速缓存来响应监视条件的发生，使得一半的地址空间被分配给第一个线程，而后半部分被分配给下一个线程。 属于第一个线程的预测生成的地址然后被定向到分配给该线程的数组的一半，并且属于第二个线程的预测生成的地址被定向到分配给该线程的数组的下一半 第二线程。 为了拆分阵列，阵列中的最高位用于唯一标识第一和第二个线程的地址。

公开(公告)号：US07000233B2

公开(公告)日：2006-02-14

申请号：US10422653

申请日：2003-04-21

申请人： David Stephen Levitan ,  Balaram Sinharoy

发明人： David Stephen Levitan ,  Balaram Sinharoy

IPC分类号： G06F9/46

CPC分类号： G06F9/3867 ,  G06F9/30189 ,  G06F9/3851

摘要： An SMT system has a single thread mode and an SMT mode. Instructions are alternately selected from two threads every clock cycle and loaded into the IFAR in a three cycle pipeline of the IFU. If a branch predicted taken instruction is detected in the branch prediction circuit in stage three of the pipeline, then in the single thread mode a calculated address from the branch prediction circuit is loaded into the IFAR on the next clock cycle. If the instruction in the branch prediction circuit detects a branch predicted taken in the SMT mode, then the selected instruction address is loaded into the IFAR on the first clock cycle following branch predicted taken detection. The calculated target address is fed back and loaded into the IFAR in the second clock cycle following branch predicted taken detection. Feedback delay effectively switches the pipeline from three stages to four stages.

摘要翻译： SMT系统具有单线程模式和SMT模式。 每个时钟周期从两个线程交替选择指令，并在IFU的三个循环管道中加载到IFAR中。 如果在流水线的第三级中在分支预测电路中检测到分支预测的指令，则在单线程模式中，来自分支预测电路的计算的地址在下一个时钟周期被加载到IFAR中。 如果分支预测电路中的指令检测到以SMT模式取得的分支预测，则在分支预测采集检测之后，所选择的指令地址在第一时钟周期被加载到IFAR中。 计算的目标地址在分支预测采集检测后的第二个时钟周期中反馈并加载到IFAR中。 反馈延迟有效地将管道从三个阶段切换到四个阶段。

公开(公告)号：US07039768B2

公开(公告)日：2006-05-02

申请号：US10424487

申请日：2003-04-25

申请人： Gregory William Alexander ,  David Stephen Levitan ,  Balaram Sinharoy

发明人： Gregory William Alexander ,  David Stephen Levitan ,  Balaram Sinharoy

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1054 ,  G06F2212/6082

摘要： A set-associative I-cache that enables early cache hit prediction and correct way selection when the processor is executing instructions of multiple threads having similar EAs. Each way of the I-cache comprises an EA Directory (EA Dir), which includes a series of thread valid bits that are individually assigned to one of the multiple threads. Particular ones of the thread valid bits are set in each EA Dir to indicate when an instruction block the thread is cached within the particular way with which the EA Dir is associated. When a cache line request for a particular thread is received, a cache hit is predicted when the EA of the request matches the EA in the EA Dir and the cache line is selected from the way associated with the EA Dir who has the thread valid bit for that thread set. Early way selection is thus achieved since the way selection only requires a check of the thread valid bits.

摘要翻译： 当处理器执行具有类似EA的多个线程的指令时，能够实现早期缓存命中预测和正确选择方法的集合关联I缓存。 I缓存的每个方式包括EA目录（EA目录），其包括单独分配给多个线程之一的一系列线程有效位。 在每个EA Dir中设置特定的线程有效位，以指示线程是否以EA Dir所关联的特定方式缓存的时间。 当接收到针对特定线程的高速缓存线请求时，当请求的EA与EA Dir中的EA匹配时，预测缓存命中，并且从与具有线程有效位的EA Dir相关联的方式中选择高速缓存行 为该线程集。 因此，由于选择方式仅需要检查线程有效位，因此实现了早期方式选择。

公开(公告)号：US06651162B1

公开(公告)日：2003-11-18

申请号：US09435065

申请日：1999-11-04

申请人： David Stephen Levitan ,  Shashank Nemawarkar ,  Balaram Sinharoy ,  William John Starke

发明人： David Stephen Levitan ,  Shashank Nemawarkar ,  Balaram Sinharoy ,  William John Starke

IPC分类号： G06F926

CPC分类号： G06F9/3806

摘要： A method of prefetching addresses includes the step of accessing a stored instruction using a current address. During the access using the current address, a target address is accessed in a branch target address cache. A stored instruction associated with the target address accessed from the branch target address cache is prefetched and the branch target address is indexed with selected bits from the address accessed from the branch target address cache.

摘要翻译： 预取地址的方法包括使用当前地址访问存储的指令的步骤。 在使用当前地址的访问期间，在分支目标地址缓存中访问目标地址。 与从分支目标地址高速缓存访​​问的目标地址相关联的存储指令被预取，并且从从分支目标地址高速缓存访​​问的地址中选择的位对索引分支目标地址进行索引。

公开(公告)号：US06484256B1

公开(公告)日：2002-11-19

申请号：US09370680

申请日：1999-08-09

申请人： David Stephen Levitan ,  Balaram Sinharoy

发明人： David Stephen Levitan ,  Balaram Sinharoy

IPC分类号： G06F900

CPC分类号： G06F9/3806 ,  G06F9/3848

摘要： Improved conditional branch instruction prediction by detecting branch aliasing in a branch history table. Each entry in an aliasing table is associated with only one of a plurality of conditional branch instructions tracked by the branch history table. Prior to executing a conditional branch instruction, outcome of the execution of the conditional branch instruction is predicted utilizing the branch history table entry associated with the conditional branch instruction. Outcome of the execution of the conditional branch instruction is also predicted utilizing the aliasing table entry associated with the conditional branch instruction. Branch aliasing is detected by comparing the prediction made utilizing the branch history table with the prediction made utilizing the aliasing table. In response to the predictions being different, a determination is made that branch aliasing occurred, and the prediction made utilizing the aliasing table is utilized for predicting the outcome of the execution of the conditional branch instruction.

摘要翻译： 通过检测分支历史表中的分支别名来改进条件分支指令预测。 混叠表中的每个条目仅与由分支历史表跟踪的多个条件转移指令中的一个相关联。 在执行条件转移指令之前，利用与条件转移指令相关联的分支历史表条目来预测条件转移指令的执行结果。 还使用与条件分支指令相关联的混叠表条目来预测条件分支指令的执行的结果。 通过将利用分支历史表进行的预测与利用混叠表进行的预测进行比较来检测分支混叠。 响应于不同的预测，确定发生分支混叠，并且使用利用混叠表进行的预测用于预测条件分支指令的执行结果。

公开(公告)号：US06823447B2

公开(公告)日：2004-11-23

申请号：US09798166

申请日：2001-03-01

申请人： Robert William Hay ,  Balaram Sinharoy

发明人： Robert William Hay ,  Balaram Sinharoy

IPC分类号： G06F900

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3846

摘要： A field is defined in branch instructions which is interpreted by software as “Hint” bits and these bits are used to signal the processor of special circumstances that may arise when doing speculative branch instruction execution to enable better branch address prediction accuracy and a reduction in link stack corruption which improves overall execution times. A programmer or compiler determines if a branch instruction usage fits in the context for a Hint action. If so, the compiler or programmer, using assembly/machine language, sets Hint bits in the branch instruction when it is compiled. If the branch is later speculatively executed, the processor decodes the Hint bits and executes and a hardware action corresponding the decode of the Hint bits. These Hints include four specific Hint actions, however, the field reserved for Hint bits is five bit wide reserving up to thirty-two specific Hint cases may be specified. These Hint cases (or Hint bits) may be interpreted differently for each type of branch instruction supported.

摘要翻译： 在分支指令中定义了一个字段，由软件将其解释为“提示”位，这些位用于向处理器发出信号，以便在进行推测性分支指令执行时可能出现的特殊情况，以实现更好的分支地址预测精度和减少链路 堆栈损坏可以提高整体执行时间。 程序员或编译器确定分支指令使用是否符合提示操作的上下文。 如果是这样，编译器或程序员使用汇编/机器语言在编译时在转移指令中设置提示位。 如果分支稍后被推测执行，则处理器对提示位进行解码并执行和与提示位的解码相对应的硬件动作。 这些提示包括四个具体的提示操作，但是，为提示位保留的字段是五位宽保留，最多可以指定三十二个特定的提示情况。 对于支持的每种类型的分支指令，可以对这些提示情况（或提示位）进行不同的解释。

公开(公告)号：US08707016B2

公开(公告)日：2014-04-22

申请号：US12024211

申请日：2008-02-01

申请人： Ravi K. Arimilli ,  Juan C. Rubio ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Juan C. Rubio ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/4843 ,  G06F9/3851

摘要： A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to common instruction boundaries. As a first partition in the set of main thread binaries executes within a first core, a second partition in the set of helper thread binaries executes within a second core, thus “warming up” the cache in the second core. When the first partition of the main completes execution, a second partition of the main core moves to the second core, and executes using the warmed up cache in the second core.

摘要翻译： 创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。 辅助线程二进制文件集和主线程二进制文件集合根据公共指令边界进行分区。 作为主线程二进制文件集合中的第一分区在第一核心内执行，该辅助线程二进制文件集中的第二分区在第二核心内执行，从而“预热”第二核心中的高速缓存。 当主要的第一分区完成执行时，主核心的第二分区移动到第二核心，并使用第二核心中的预热高速缓存执行。

公开(公告)号：US08612730B2

公开(公告)日：2013-12-17

申请号：US12796124

申请日：2010-06-08

申请人： Ronald P. Hall ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Balaram Sinharoy ,  Zhong Liang Wang

发明人： Ronald P. Hall ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Balaram Sinharoy ,  Zhong Liang Wang

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/327 ,  G06F11/3466 ,  G06F2201/865 ,  G06F2201/88

摘要： A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.

摘要翻译： 一种用于管理程序中的指令的运行的方法和数据处理系统。 数据处理系统的处理器接收监视单元的监视指令。 处理器确定一组辅助线程的至少一个辅助线程是否可用作辅助线程。 响应于确定所述一组次要线程的至少一个辅助线程可用作辅助线程，所述处理器从所述辅助线程组中选择所述至少一个辅助线程以成为所述辅助线程。 处理器将程序中指令的运行情况从主线程更改为辅助线程。