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1.发明授权Method and system for software control of hardware branch prediction mechanism in a data processor 失效数据处理器中硬件分支预测机制的软件控制方法与系统公开(公告)号：US06662360B1
公开(公告)日：2003-12-09
申请号：US09407105
申请日：1999-09-27
申请人： Robert William Hay , James Allan Kahle , Brian R. Konigsburg , David Stephen Levitan , Balaram Sinharoy
发明人： Robert William Hay , James Allan Kahle , Brian R. Konigsburg , David Stephen Levitan , Balaram Sinharoy
IPC分类号： G06F944
CPC分类号： G06F9/3846 , G06F9/3848
摘要： A method and system is disclosed for software manipulation of hardware prediction mechanism in a data processor with software prediction. The hardware branch prediction mechanism is enhanced with at least two bits for path prediction. These bits are settable by a software and are capable of overriding the hardware branch prediction mechanism. Branch prediction information is encoded into a branch instruction in the software. This information includes a pre-determined value for each bit. Finally, a branch path of said instruction is predicted based on the value of the bits.
摘要翻译： 公开了一种用于软件预测的数据处理器中硬件预测机制的软件操纵的方法和系统。 用于路径预测的至少两个比特来增强硬件分支预测机制。 这些位可由软件设置，并能够覆盖硬件分支预测机制。 分支预测信息被编码成软件中的分支指令。 该信息包括每个位的预定值。 最后，基于比特的值来预测所述指令的分支路径。
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2.发明申请公开(公告)号：US20080276080A1
公开(公告)日：2008-11-06
申请号：US12171370
申请日：2008-07-11
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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公开(公告)号：US06279105B1
公开(公告)日：2001-08-21
申请号：US09173039
申请日：1998-10-15
IPC分类号： G06F1300
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3861
摘要： In a branch instruction target address cache, an entry associated with a fetched block of instructions includes a target address of a branch instruction residing in the next sequential block of instructions. The entry will include a sequential address associated with the branch instruction and a prediction of whether the target address is taken or not taken.
摘要翻译： 在分支指令目标地址高速缓存中，与获取的指令块相关联的条目包括驻留在下一个顺序指令块中的分支指令的目标地址。 条目将包括与分支指令相关联的顺序地址以及是否采取目标地址的预测。
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4.发明授权Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread 失效具有结果数据延迟路径的同时多线程处理器，用于调整输入到相应线程的流水线长度公开(公告)号：US07000233B2
公开(公告)日：2006-02-14
申请号：US10422653
申请日：2003-04-21
IPC分类号： G06F9/46
CPC分类号： G06F9/3867 , G06F9/30189 , G06F9/3851
摘要： An SMT system has a single thread mode and an SMT mode. Instructions are alternately selected from two threads every clock cycle and loaded into the IFAR in a three cycle pipeline of the IFU. If a branch predicted taken instruction is detected in the branch prediction circuit in stage three of the pipeline, then in the single thread mode a calculated address from the branch prediction circuit is loaded into the IFAR on the next clock cycle. If the instruction in the branch prediction circuit detects a branch predicted taken in the SMT mode, then the selected instruction address is loaded into the IFAR on the first clock cycle following branch predicted taken detection. The calculated target address is fed back and loaded into the IFAR in the second clock cycle following branch predicted taken detection. Feedback delay effectively switches the pipeline from three stages to four stages.
摘要翻译： SMT系统具有单线程模式和SMT模式。 每个时钟周期从两个线程交替选择指令，并在IFU的三个循环管道中加载到IFAR中。 如果在流水线的第三级中在分支预测电路中检测到分支预测的指令，则在单线程模式中，来自分支预测电路的计算的地址在下一个时钟周期被加载到IFAR中。 如果分支预测电路中的指令检测到以SMT模式取得的分支预测，则在分支预测采集检测之后，所选择的指令地址在第一时钟周期被加载到IFAR中。 计算的目标地址在分支预测采集检测后的第二个时钟周期中反馈并加载到IFAR中。 反馈延迟有效地将管道从三个阶段切换到四个阶段。
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公开(公告)号：US07984280B2
公开(公告)日：2011-07-19
申请号：US12171370
申请日：2008-07-11
IPC分类号： G06F9/00
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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6.发明授权Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment 失效通过在同时多线程处理环境中逻辑分割分支历史表和预测目标地址缓存来进行线程专用分支预测公开(公告)号：US07120784B2
公开(公告)日：2006-10-10
申请号：US10425064
申请日：2003-04-28
CPC分类号： G06F9/3806 , G06F9/30189 , G06F9/3844 , G06F9/3851
摘要： Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.
摘要翻译： 分支预测逻辑被增强以提供用于某些条件的监视功能，其指示使用单独的BHT和预测的目标地址高速缓存将为分支预测提供更好的结果。 分支预测逻辑通过逻辑分割BHT和计数高速缓存来响应监视条件的发生，使得一半的地址空间被分配给第一个线程，而后半部分被分配给下一个线程。 属于第一个线程的预测生成的地址然后被定向到分配给该线程的数组的一半，并且属于第二个线程的预测生成的地址被定向到分配给该线程的数组的下一半 第二线程。 为了拆分阵列，阵列中的最高位用于唯一标识第一和第二个线程的地址。
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公开(公告)号：US08943301B2
公开(公告)日：2015-01-27
申请号：US13101650
申请日：2011-05-05
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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公开(公告)号：US07487334B2
公开(公告)日：2009-02-03
申请号：US11050350
申请日：2005-02-03
IPC分类号： G06F9/34
摘要： Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch prior to writing the branch into a Level 1 (L1) cache to provide a pre-decoded branch, and then writing the pre-decoded branch into the L1 cache. By pre-calculating matters relating to the targets of branches before the branches are written into the L1 cache, for example, by re-encoding relative branches as absolute branches, a reduction in branch redirect delay can be achieved, thus providing a substantial improvement in overall processor performance.
摘要翻译： 用于确定数据处理系统中分支目标的方法，系统和计算机程序产品。 一种用于确定数据处理系统中的分支的目标的方法包括在将分支写入级别1（L1）高速缓存之前执行与确定分支的目标有关的至少一个预计算，以提供预解码分支 ，然后将预解码的分支写入L1高速缓存。 通过在将分支写入L1高速缓存之前预先计算与分支目标相关的事项，例如通过将相关分支重新编码为绝对分支，可以实现分支重定向延迟的减少，从而提供了显着的改进 整体处理器性能。
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9.发明授权Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor 失效用于在超标量微处理器中同步并行管线的方法和装置公开(公告)号：US06385719B1
公开(公告)日：2002-05-07
申请号：US09345719
申请日：1999-06-30
IPC分类号： G06F938
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher. Individual instructions within the fetched group for the branch pipeline are assigned a concatenated version (group tag concatenated with instruction lane) of the transfer tag which is used to match on requests to flush any newer instructions. All potential instruction or Internal Operation latches in the decode pipeline must perform a match and if a match is encountered, all valid bits associated with newer instructions or internal operations upstream from the match are cleared. The transfer tag representing the next instruction to be processed in the branch pipeline is passed to the Instruction Dispatch Unit. The Instruction Dispatch Unit queries the branch pipeline to compare its transfer tag with transfer tags of instructions in the branch pipeline. If the transfer tag matches a branch instruction tag the Instruction Decode Unit is stalled until the branch instruction is processed thus, providing a synchronizing method for the parallel pipelines.
摘要翻译： 传送标签由指令提取单元生成，并在指令流水线中传送给解码单元，每个指令组由读取器在分支预测期间取出。 为分支流水线提取的组中的单独指令被分配用于匹配在刷新任何较新指令的请求上的传送标签的级联版本（组标签与指令通道连接）。 解码流水线中的所有潜在指令或内部操作锁存器必须执行匹配，并且如果遇到匹配，将清除与较新指令相关联的所有有效位或匹配上游的内部操作。 表示在分支管线中要处理的下一条指令的传送标签被传递到指令调度单元。 指令调度单元查询分支流水线以将其传输标签与分支流水线中的指令的传输标签进行比较。 如果转移标签与分支指令标签匹配，则指令解码单元停止，直到处理分支指令为止，为并行管线提供同步方法。
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公开(公告)号：US20110213951A1
公开(公告)日：2011-09-01
申请号：US13101650
申请日：2011-05-05
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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