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1.发明申请公开(公告)号：US20080276080A1
公开(公告)日：2008-11-06
申请号：US12171370
申请日：2008-07-11
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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公开(公告)号：US07984280B2
公开(公告)日：2011-07-19
申请号：US12171370
申请日：2008-07-11
IPC分类号： G06F9/00
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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公开(公告)号：US08943301B2
公开(公告)日：2015-01-27
申请号：US13101650
申请日：2011-05-05
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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公开(公告)号：US20110213951A1
公开(公告)日：2011-09-01
申请号：US13101650
申请日：2011-05-05
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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5.发明授权Methods and systems for storing branch information in an address table of a processor 失效用于将分支信息存储在处理器的地址表中的方法和系统公开(公告)号：US07426631B2
公开(公告)日：2008-09-16
申请号：US11049014
申请日：2005-02-02
CPC分类号： G06F9/3806
摘要： Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法和系统。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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6.发明授权Method and logical apparatus for managing processing system resource use for speculative execution 失效用于管理用于投机执行的处理系统资源使用的方法和逻辑装置公开(公告)号：US07890738B2
公开(公告)日：2011-02-15
申请号：US11039498
申请日：2005-01-20
CPC分类号： G06F9/5011 , G06F9/3844 , G06F9/3851 , G06F2209/507 , Y02D10/22
摘要： A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is low. The resource control applied may be the number of instruction fetches allocated to the thread or the number of execution time slices. Alternatively, or in combination, the size of a prefetch instruction storage allocated to the thread may be limited. The control condition may be comparison of the number of correct or incorrect speculations to a threshold, comparison of the number of correct to incorrect speculations, or a more complex evaluator such as the size of a ratio of incorrect to total speculations.
摘要翻译： 用于管理用于推测性执行的处理系统资源使用的方法和逻辑装置降低与程序指令的无效推测执行相关联的功率和性能负担。 投机执行效率的度量用于减少分配给线程的资源，同时投机效率低。 应用的资源控制可以是分配给线程的指令获取的数量或执行时间片的数量。 或者或组合地，分配给线程的预取指令存储器的大小可能受到限制。 控制条件可以是正确的或不正确的猜测的数量与阈值的比较，正确到不正确的猜测的数量的比较，或比较复杂的评估者，比如不正确比例与总猜测的比例。
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7.发明授权Managing load and store operations using a storage management unit with data flow architecture 失效使用具有数据流架构的存储管理单元管理加载和存储操作公开(公告)号：US06938148B2
公开(公告)日：2005-08-30
申请号：US09737342
申请日：2000-12-15
CPC分类号： G06F9/3828 , G06F9/3816 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3832 , G06F9/3834 , G06F9/3851
摘要： A Storage Reference Buffer (SRB) designed as an autonomous unit for all Store operations that transfer data from the execution unit of a processor to the memory hierarchy and Load operations that transfer data from the memory hierarchy to the execution unit of the processor. The SRB partitions up the Load and Store operations into several smaller operations in order to perform them in parallel with other Load and Store requests. System elements are included to determine unambiguously which of these Load and Store operations may be performed without waiting for prior operations to be completed. The SRB also includes system elements to detect whether requests may be satisfied by existing entries in the SRB without having to access the cache. The SRB is operated as a content addressable memory. Load request are simultaneously launched to cache and to the SRB with the Cache request being canceled if the Load request may be satisfied by an SRB entry.
摘要翻译： 存储引用缓冲器（SRB）被设计为用于将数据从处理器的执行单元传送到存储器层级的所有存储操作的自主单元，以及将数据从存储器层次传送到处理器的执行单元的负载操作。 SRB将加载和存储操作分成几个较小的操作，以便与其他加载和存储请求并行执行它们。 包括系统元素以明确地确定可以在不等待先前操作完成的情况下执行这些加载和存储操作中的哪一个。 SRB还包括用于检测请求是否可以通过SRB中的现有条目来满足而不必访问高速缓存的系统元件。 SRB作为内容可寻址存储器运行。 如果Load请求可能被SRB条目所满足，加载请求将同时启动到缓存和SRB，缓存请求被取消。
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公开(公告)号：US20100262813A1
公开(公告)日：2010-10-14
申请号：US12423608
申请日：2009-04-14
申请人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/30003 , G06F8/433 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3844 , G06F9/3846 , G06F9/3855
摘要： Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.
摘要翻译： 在处理器中提供用于检测和处理短前进分支转换候选的机制。 机制识别计算机代码中的条件分支，并确定短向前向条件分支是否要转换为非分支条件指令序列。 此外，机制将条件分支转换为包括解决指令和取决于解析指令的一个或多个条件指令的非分支条件指令序列。 此外，这些机制代替计算机代码中的条件分支执行非分支条件指令序列，并且基于非分支条件指令序列的执行生成计算机代码的输出。
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