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    Method and device for high performance regular expression pattern matching
    1.
    发明授权
    Method and device for high performance regular expression pattern matching 有权
    用于高性能正则表达式匹配的方法和装置

    公开(公告)号：US07702629B2

    公开(公告)日：2010-04-20

    申请号：US11293619

    申请日：2005-12-02

    申请人： Ron K. Cytron ,  David Edward Taylor ,  Benjamin Curry Brodie

    发明人： Ron K. Cytron ,  David Edward Taylor ,  Benjamin Curry Brodie

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30985 ,  Y10S707/99936

    摘要： Disclosed herein is an improved architecture for regular expression pattern matching. Improvements to pattern matching deterministic finite automatons (DFAs) that are described by the inventors include a pipelining strategy that pushes state-dependent feedback to a final pipeline stage to thereby enhance parallelism and throughput, augmented state transitions that track whether a transition is indicative of a pattern match occurring thereby reducing the number of necessary states for the DFA, augmented state transition that track whether a transition is indicative of a restart to the matching process, compression of the DFA's transition table, alphabet encoding for input symbols to equivalence class identifiers, the use of an indirection table to allow for optimized transition table memory, and enhanced scalability to facilitate the ability of the improved DFA to process multiple input symbols per cycle.

    摘要翻译： 这里公开了用于正则表达式模式匹配的改进的架构。 由发明人描述的对模式匹配确定性有限自动机（DFA）的改进包括流水线策略，其将状态相关反馈推送到最终流水线级，从而增强并行度和吞吐量，增强的状态转换，跟踪转移是否指示 模式匹配发生，从而减少了DFA的必要状态数量，增强状态转换，跟踪转移是否指示重新启动到匹配过程，DFA转换表的压缩，输入符号的字母编码等价类标识符， 使用间接表来允许优化的转换表存储器，以及增强的可扩展性，以便于改进的DFA在每个周期处理多个输入符号的能力。

    Method and device for high performance regular expression pattern matching
    2.
    发明授权
    Method and device for high performance regular expression pattern matching 有权
    用于高性能正则表达式匹配的方法和装置

    公开(公告)号：US07945528B2

    公开(公告)日：2011-05-17

    申请号：US12703388

    申请日：2010-02-10

    申请人： Ron K. Cytron ,  David Edward Taylor ,  Benjamin Curry Brodie

    发明人： Ron K. Cytron ,  David Edward Taylor ,  Benjamin Curry Brodie

    IPC分类号： G06F15/00 ,  G06F15/18

    CPC分类号： G06F17/30985 ,  Y10S707/99936

    摘要： Disclosed herein is an improved architecture for regular expression pattern matching. Improvements to pattern matching deterministic finite automatons (DFAs) that are described by the inventors include a pipelining strategy that pushes state-dependent feedback to a final pipeline stage to thereby enhance parallelism and throughput, augmented state transitions that track whether a transition is indicative of a pattern match occurring thereby reducing the number of necessary states for the DFA, augmented state transition that track whether a transition is indicative of a restart to the matching process, compression of the DFA's transition table, alphabet encoding for input symbols to equivalence class identifiers, the use of an indirection table to allow for optimized transition table memory, and enhanced scalability to facilitate the ability of the improved DFA to process multiple input symbols per cycle.

    摘要翻译： 这里公开了用于正则表达式模式匹配的改进的架构。 由发明人描述的对模式匹配确定性有限自动机（DFA）的改进包括流水线策略，其将状态相关反馈推送到最终流水线级，从而增强并行度和吞吐量，增强的状态转换，跟踪转移是否指示 模式匹配发生，从而减少了DFA的必要状态数量，增强状态转换，跟踪转移是否指示重新启动到匹配过程，DFA转换表的压缩，输入符号的字母编码等价类标识符， 使用间接表来允许优化的转换表存储器，以及增强的可扩展性，以便于改进的DFA在每个周期处理多个输入符号的能力。

    Method and Device for High Performance Regular Expression Pattern Matching
    3.
    发明申请
    Method and Device for High Performance Regular Expression Pattern Matching 有权
    高性能正则表达式模式匹配的方法和装置

    公开(公告)号：US20100198850A1

    公开(公告)日：2010-08-05

    申请号：US12703388

    申请日：2010-02-10

    申请人： Ron K. Cytron ,  David Edward Taylor ,  Benjamin Curry Brodie

    发明人： Ron K. Cytron ,  David Edward Taylor ,  Benjamin Curry Brodie

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30985 ,  Y10S707/99936

    摘要： Disclosed herein is an improved architecture for regular expression pattern matching. Improvements to pattern matching deterministic finite automatons (DFAs) that are described by the inventors include a pipelining strategy that pushes state-dependent feedback to a final pipeline stage to thereby enhance parallelism and throughput, augmented state transitions that track whether a transition is indicative of a pattern match occurring thereby reducing the number of necessary states for the DFA, augmented state transition that track whether a transition is indicative of a restart to the matching process, compression of the DFA's transition table, alphabet encoding for input symbols to equivalence class identifiers, the use of an indirection table to allow for optimized transition table memory, and enhanced scalability to facilitate the ability of the improved DFA to process multiple input symbols per cycle.

    摘要翻译： 这里公开了用于正则表达式模式匹配的改进的架构。 由发明人描述的对模式匹配确定性有限自动机（DFA）的改进包括流水线策略，其将状态相关反馈推送到最终流水线级，从而增强并行度和吞吐量，增强的状态转换，跟踪转移是否指示 模式匹配发生，从而减少了DFA的必要状态数量，增强状态转换，跟踪转移是否指示重新启动到匹配过程，DFA转换表的压缩，输入符号的字母编码等价类标识符， 使用间接表来允许优化的转换表存储器，以及增强的可扩展性，以便于改进的DFA在每个周期处理多个输入符号的能力。

    System and method for solving monotone information propagation problems
    5.
    发明授权
    System and method for solving monotone information propagation problems 失效
    解决单调信息传播问题的系统和方法

    公开(公告)号：US5327561A

    公开(公告)日：1994-07-05

    申请号：US763099

    申请日：1991-09-20

    申请人： Jong-Deok Choi ,  Ron K. Cytron ,  Jeanne Ferrante

    发明人： Jong-Deok Choi ,  Ron K. Cytron ,  Jeanne Ferrante

    IPC分类号： G06F9/45 ,  G06F9/00 ,  G06F9/44

    CPC分类号： G06F8/433

    摘要： A method and system is provided for constructing sparse evaluation graphs for forward or backward monotone data flow problems. The sparse graph combines information as early as possible, yet directly connects nodes that generate and use information. This allows problems from the large, general class of monotone data flow problems to enjoy the advantages of solutions based on Static Single Assignment (SSA) form.The present invention includes a compiler configured to transform a source program into optimized executable code. The compiler contains an optimizer which is configured to optimize the source program, in which the source program and optimization program are represented by a data flow framework. The optimizer includes a sparse evaluation graph generator which generates a sparse evaluation graph and an evaluator connected to evaluate the sparse evaluation graph in relation to the data flow framework.

    摘要翻译： 提供了一种构建用于正向或反向单调数据流问题的稀疏评估图的方法和系统。 稀疏图尽可能早地组合信息，但是直接连接生成和使用信息的节点。 这样就可以从庞大的一般类别的单调数据流问题中获得基于静态单一分配（SSA）形式的解决方案的优势。 本发明包括被配置为将源程序转换成优化的可执行代码的编译器。 编译器包含优化器，该优化器被配置为优化源程序，其中源程序和优化程序由数据流框架表示。 优化器包括稀疏评估图生成器，其产生稀疏评估图和连接的评估器，以评估与数据流框架相关的稀疏评估图。

    Intelligent data storage and processing using FPGA devices
    6.
    发明授权
    Intelligent data storage and processing using FPGA devices 有权
    使用FPGA器件进行智能数据存储和处理

    公开(公告)号：US08751452B2

    公开(公告)日：2014-06-10

    申请号：US13345011

    申请日：2012-01-06

    申请人： Roger D. Chamberlain ,  Mark Allen Franklin ,  Ronald S. Indeck ,  Ron K. Cytron ,  Sharath R. Cholleti

    发明人： Roger D. Chamberlain ,  Mark Allen Franklin ,  Ronald S. Indeck ,  Ron K. Cytron ,  Sharath R. Cholleti

    IPC分类号： G06F17/00

    CPC分类号： G06F9/44505 ,  G06F3/0601 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/067 ,  G06F3/0683 ,  G06F9/4881 ,  G06F17/00 ,  G06F17/30477 ,  G06F21/602 ,  G06F21/72 ,  G06F21/76 ,  G06F21/85 ,  G06F2003/0692 ,  G06Q40/06

    摘要： A re-configurable logic device such as a field programmable gate array (FPGA) can be used to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data processing engines, the plurality of pipelined data processing engines including a data reduction engine, the plurality of pipelined data processing engines being configured to perform processing operations, wherein the pipeline comprises a multi-functional pipeline, and wherein the re-configurable logic device is further configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline.

    摘要翻译： 可以使用诸如现场可编程门阵列（FPGA）的可重新配置的逻辑设备来部署数据处理流水线，该管线包括多个流水线数据处理引擎，该多个流水线数据处理引擎包括数据缩减引擎， 所述多个流水线数据处理引擎被配置为执行处理操作，其中所述流水线包括多功能流水线，并且其中所述可重配置逻辑设备还被配置为可控制地激活或停用流水线数据处理引擎中的每个流水线 响应于控制指令并由此定义管道的功能，每个管道功能是流水线中每个激活的流水线数据处理引擎的组合功能。