摘要:
Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream. Counterpart modulation decoders and decoding apparatus are also described.
摘要:
A circuit for a partial-response, maximum likelihood (PRML) magnetic recording channel stretches and shrinks pulses in particular write-data sequences. The circuit maintains precise tracking in the delays among multiple signals by sending them through the same number of identical circuits on the same chip. An external digital code varies the amount of delay in a clock signal so as to stretch and shrink the data pulses by different amounts.