公开(公告)号：US07626520B2

公开(公告)日：2009-12-01

申请号：US12042862

申请日：2008-03-05

申请人： Makoto Noda

发明人： Makoto Noda

IPC分类号： H03M5/00

CPC分类号： G11B20/1426 ,  G11B2020/1446 ,  G11B2020/1449 ,  G11B2020/1473 ,  H03M5/145

摘要： An encoding method is disclosed for use with an encoding apparatus for carrying out variable-length conversion encoding involving a look-ahead operation of at least either one information word or one code word upon encoding. The encoding method includes the step of performing conversion encoding in such a manner as to permit decoding of encoded words in units of a code word.

摘要翻译： 公开了一种与编码装置一起使用的编码方法，用于在编码时执行涉及至少一个信息字或一个码字的预读操作的可变长度转换编码。 编码方法包括以允许以码字为单位对编码字进行解码的方式进行转换编码的步骤。

公开(公告)号：US07274312B2

公开(公告)日：2007-09-25

申请号：US11359453

申请日：2006-04-06

申请人： William G. Bliss ,  Andrei Vityaev ,  Razmik Karabed

发明人： William G. Bliss ,  Andrei Vityaev ,  Razmik Karabed

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B20/10009 ,  G11B20/1833 ,  G11B2020/1446 ,  H03M5/145 ,  H03M13/093

摘要： An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b. . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.

摘要翻译： 一种装置具有转换电路，预编码器电路和选择电路。 转换电路转换用户数据b 1，b 2，b。 。 。 对于编码序列c 0，c 1，c 2，...， 。 。 c 。 选择电路在编码序列c 0 0，c 1，c 2 2中选择c <0> 0 。 。 。 使得预编码器电路的输出具有小于转换的最大数量q。 转换电路可以包括用于转换用户数据b 1，b 2，b 3 3的编码器电路。 。 。 c 到序列c 1，c 2。 。 。 以及向序列c 1，c 2 2加上c 0的转换最小化电路。 。 。 c 。 该装置可以具有电路，用于将至少一个额外的位（其可以是奇偶校验位）添加到编码序列c 0，c 1，c 2 。 。 。 c 。

公开(公告)号：US07196999B2

公开(公告)日：2007-03-27

申请号：US09814379

申请日：2001-03-21

申请人： Masayuki Hattori ,  Jun Murayama ,  Toshiyuki Miyauchi

发明人： Masayuki Hattori ,  Jun Murayama ,  Toshiyuki Miyauchi

IPC分类号： G11B5/09

CPC分类号： H03M13/6325 ,  G11B20/10009 ,  G11B20/1426 ,  G11B20/1866 ,  G11B2020/1434 ,  G11B2020/1446 ,  H03M5/14 ,  H03M13/27 ,  H03M13/2957 ,  H03M13/2972 ,  H03M13/45 ,  H03M13/6343

摘要： A method and apparatus for recording or reproducing data in which high performance encoding and a high efficiency decoding are realized to lower the decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes, in a recording system, a modulation encoder 52 for modulation encoding input data in a predetermined fashion and an interleaver 53 for interleaving data supplied from the modulation encoder 52 to re-array the data sequence. The magnetic recording and/or reproducing apparatus 50 also includes, in a reproducing system, a first deinterleaver for interleaving the input data for re-arraying the data sequence so that the bit sequence of data re-arrayed by the interleaver 53 will be restored to its original bit sequence, a modulation SISO decoder for modulation decoding data supplied from the first deinterleaver and a second deinterleaver for interleaving data corresponding to a difference value between data output by the modulation SISO decoder and data output by the first deinterleaver to re-array the data sequence of the difference data.

摘要翻译： 用于记录或再现其中实现高性能编码和高效率解码以降低解码错误率的数据的方法和装置。 磁记录和/或再现装置50在记录系统中包括用于以预定方式对输入数据进行调制编码的调制编码器52和用于交织从调制编码器52提供的数据的交织器53以重新排列数据序列。 磁记录和/或再现装置50还包括在再现系统中的第一解交织器，用于交织用于重新排列数据序列的输入数据，使得由交织器53重新排列的数据的位序列将被恢复到 其原始比特序列，用于从第一去交织器提供的调制解码数据的调制SISO解码器和用于对应于由调制SISO解码器输出的数据与由第一解交织器输出的数据之间的差值相对应的数据的第二解交织器，用于重新排列 差异数据的数据序列。

公开(公告)号：US06493846B1

公开(公告)日：2002-12-10

申请号：US09323703

申请日：1999-06-01

申请人： Masaharu Kondo ,  Seiichi Mita

发明人： Masaharu Kondo ,  Seiichi Mita

IPC分类号： H03M1303

CPC分类号： G11B20/1833 ,  G11B20/1426 ,  G11B2020/1446 ,  H03M13/31

摘要： A signal processing apparatus capable of reducing burst error generation, and a highly reliable data recording/reproducing apparatus using this signal processing apparatus. This signal processing apparatus has a simple error detection/correction circuit provided just before a modulated code demodulator, thereby correcting error of a pattern easy to occur in a maximum likelihood decoder. The simple error detection/correction circuit is an error detection/correction circuit using a linear error correction code, for example, an error correction code (CRCC) formed of a cyclic code. Thus the number of burst errors after the modulated code demodulator can be decreased.

摘要翻译： 能够减少突发错误产生的信号处理装置，以及使用该信号处理装置的高度可靠的数据记录/再现装置。 该信号处理装置具有在调制码解调器之前提供的简单的错误检测/校正电路，从而校正容易发生在最大似然解码器中的图案的误差。 简单的错误检测/校正电路是使用线性纠错码（例如由循环码形成的纠错码（CRCC））的错误检测/校正电路。 因此，可以减少调制码解调器之后的突发错误的数量。

公开(公告)号：US6130629A

公开(公告)日：2000-10-10

申请号：US205319

申请日：1998-12-04

申请人： Pervez M. Aziz ,  Patrick W. Kempsey ,  Srinivasan Surendran

发明人： Pervez M. Aziz ,  Patrick W. Kempsey ,  Srinivasan Surendran

IPC分类号： G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  H03M7/14 ,  H03M13/00 ,  H03M13/23 ,  H03M13/25 ,  H04L1/00 ,  H04L25/497 ,  H03M7/00

CPC分类号： H04L1/0057 ,  G11B20/1426 ,  H04L1/0041 ,  H04L1/0045 ,  G11B2020/1434 ,  G11B2020/1446 ,  G11B2020/1449

摘要： A system and method employing a rate 24/25 (0,9) code constructed in accordance with a data byte interleaved with a rate 16/17 (0,5) codeword formed from two data bytes limits the number of consecutive zeros seen by a channel to nine. The 16/17 (0,5) codeword is formed from the two data bytes in accordance with a set of pivot bits and a set of corrections for predefined code violations. The additional data byte is interleaved into the 16/17 (0,5) codeword by splitting the byte into a pair of portions and inserting the portions into the 16/17 (0,5) codeword at locations adjacent to predefined ones of the pivot bits. The rate 24/25 (0,9) code is suitable for magnetic or similar recording media and may be employed in partial response maximum likelihood read channels. A feature of the constructed code is a high transition density which allows for more frequent timing and gain control updates, which results in lower required channel input signal to noise ratio for a given channel performance.

摘要翻译： 使用根据与由两个数据字节形成的速率16/17（0.5）码字交织的数据字节构成的速率24/25（0,9）码的系统和方法限制了由 渠道九。 16/17（0,5）码字是根据一组枢轴比特和一组用于预定义代码违例的校正从两个数据字节形成的。 通过将该字节分割成一对部分并将这些部分插入邻近预定义枢纽的位置的16/17（0,5）码字中，附加数据字节被交织到16/17（0,5）码字中 位。 速率24/25（0,9）代码适用于磁性或类似的记录介质，并可用于部分响应最大似然读取通道。 构造的代码的特征是高转换密度，其允许更频繁的定时和增益控制更新，这导致给定信道性能所需的信道输入信噪比更低。

公开(公告)号：US6097321A

公开(公告)日：2000-08-01

申请号：US69822

申请日：1998-04-30

申请人： Necip Sayiner

发明人： Necip Sayiner

IPC分类号： G06F11/10 ,  G06F11/00 ,  G11B20/14 ,  G11B20/18 ,  H03M13/23 ,  H04L1/00 ,  H03M7/00

CPC分类号： G11B20/1426 ,  G11B2020/1434 ,  G11B2020/1446

摘要： A punctured maximum transition run (PMTR) code includes transition-allowed bit slots and transition-disallowed bit slots. Each of the transition-allowed bit slots is a bit slot in which a bit representing a third consecutive transition of a logic signal can occur whereas each of the transition-disallowed bit slots is a bit slot in which a bit representing a third consecutive transition of a logic signal cannot occur. There are at least two transition-allowed bit slots which are adjacent to each other. The transition occurs from a high logic level to a low logic level, or from a low logic level to a high logic level.

摘要翻译： 穿孔最大过渡运行（PMTR）代码包括转换允许位时隙和转换不允许的位时隙。 每个转换允许位时隙是一个位时隙，其中可以发生表示逻辑信号的第三个连续转换的位，而每个转换不允许的位时隙是一个位时隙，其中表示第 不能发生逻辑信号。 至少有两个彼此相邻的转换允许位时隙。 转换从高逻辑电平到低逻辑电平，或从低逻辑电平发生到高逻辑电平。

公开(公告)号：US6035435A

公开(公告)日：2000-03-07

申请号：US940869

申请日：1997-09-30

申请人： Shih-Ming Shih ,  Hemant Thapar

发明人： Shih-Ming Shih ,  Hemant Thapar

IPC分类号： G06F11/10 ,  G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  H03M5/14 ,  H03M13/31 ,  H03M13/41 ,  H03M13/23

CPC分类号： G11B20/1426 ,  G11B20/10009 ,  H03M13/31 ,  H03M5/145 ,  G11B2020/1434 ,  G11B2020/1446

摘要： A system and method are described for avoiding catastrophic error sequences in a media code sequence of symbols for data storage on a storage medium according to EPRML. The system and method includes modulation encoding user data which is to be stored on the storage medium using a modulation encoder. The modulation encoder outputs a channel code modulation output symbol sequence. The modulation code is defined according to a modulation criteria wherein the set of all possible modulation output symbol sequences is constrained in a manner which excludes certain excluded modulation output symbol sequences. A precoder precodes the channel code modulation output symbol sequence according to a precoding transfer function. The precoding transfer function transforms the channel code modulation output symbol sequence into a media code sequence of symbols and the preceding transfer function is defined so that when modulation encoding is performed according to the modulation criteria, the media code sequence of symbols is constrained to exclude EPRML catastrophic error sequences of greater than a determined length. The combination of the modulation encoding and the precoding prevents the media code sequence of symbols from including EPRML catastrophic error sequences greater than the determined length.

摘要翻译： 描述了一种系统和方法，用于在根据EPRML的存储介质上的数据存储的媒体代码序列序列中避免灾难性错误序列。 该系统和方法包括使用调制编码器对要存储在存储介质上的用户数据进行调制编码。 调制编码器输出信道码调制输出符号序列。 根据调制准则来定义调制码，其中所有可能的调制输出符号序列的集合以排除某些被排除的调制输出符号序列的方式被约束。 预编码器根据预编码传递函数对信道码调制输出符号序列进行预编码。 预编码传递函数将信道码调制输出符号序列变换成符号的媒体码序列，并且定义前述传递函数，使得当根据调制准则执行调制编码时，限制符号的媒体码序列以排除EPRML 大于确定长度的灾难性错误序列。 调制编码和预编码的组合防止符号的媒体码序列包括大于所确定的长度的EPRML灾难性错误序列。

公开(公告)号：US5537112A

公开(公告)日：1996-07-16

申请号：US180567

申请日：1994-01-12

申请人： Kinhing P. Tsang

发明人： Kinhing P. Tsang

IPC分类号： G06T9/00 ,  G11B20/10 ,  G11B20/14 ,  H03M5/14 ,  H03M7/00

CPC分类号： G11B20/1426 ,  G06T9/005 ,  H03M5/145 ,  G11B20/10009 ,  G11B2020/143 ,  G11B2020/1434 ,  G11B2020/1446

摘要： A method apparatus for encoding segments having a selected number of ordered bits of binary data from a sequence of ordered bits of binary data into corresponding codewords having a selected number of ordered bits of binary data, such that the sequence of ordered bits of binary data is encoded into a sequence of codewords. The apparatus comprises a receiver device for receiving the segments; a separating device for separating the selected number of ordered bits of binary data of each segment into a corresponding first group and a corresponding second group; an encoder mapping device for mapping each first group into a corresponding word having a selected number of ordered bits of binary data; and an interleaving device for interleaving the bits of each corresponding second group with the selected number of ordered bits of binary data of each corresponding word to obtain the corresponding codewords.

摘要翻译： 一种用于将具有二进制数据的有序位的选定数量的二进制数据的段的段编码成二进制数据的有序位的序列到具有选定数量的二进制数据的有序位的对应码字的方法装置，使得二进制数据的有序位序列为 编码成码字序列。 该装置包括用于接收段的接收装置; 分离装置，用于将每个段的二进制数据的选定数量的有序位分离成对应的第一组和对应的第二组; 编码器映射设备，用于将每个第一组映射到具有选定数量的二进制数据的有序位的对应字; 以及交织装置，用于将每个对应的第二组的比特与每个相应字的二进制数据的所选择的数量的比特进行交织，以获得相应的码字。

公开(公告)号：US07876516B2

公开(公告)日：2011-01-25

申请号：US12351747

申请日：2009-01-09

申请人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

发明人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

IPC分类号： G11B5/09 ,  G11B20/14

CPC分类号： G11B20/1833 ,  G11B20/1201 ,  G11B20/1866 ,  G11B2020/1287 ,  G11B2020/1289 ,  G11B2020/1446 ,  G11B2020/1836 ,  G11B2220/93 ,  H03M13/27 ,  H03M13/271

摘要： For writing data to multi-track tape, a received data set is received and segmented into unencoded subdata sets, each comprising an array having K2 rows and K1 columns. For each unencoded subdata set, N1-K1 C1-parity bytes are generated for each row and N2-K2 C2-parity bytes are generated for each column. The C1 and C2 parity bytes are appended to the ends of the row and column, respectively, to form encoded C1 and C2 codewords, respectively. All of the C1 codewords per data set are endowed with a specific codeword header to form a plurality of partial codeword objects (PCOs). Each PCO is mapped onto a logical data track according to information within the header. On each logical data track, adjacent PCOs are merged to form COs which are modulation encoded and mapped into synchronized COs. Then T synchronized COs are written simultaneously to the data tape where T is the number of concurrent active tracks on the data tape.

摘要翻译： 为了将数据写入多轨磁带，接收到的数据集并被分割成未编码的子数据集，每个子​​集包括具有K2行和K1列的阵列。 对于每个未编码的子数据集，为每行生成N1-K1 C1-奇偶校验字节，并为每列生成N2-K2 C2-奇偶校验字节。 C1和C2奇偶校验字节分别附加到行和列的末端，分别形成编码的C1和C2码字。 每个数据集的所有C1码字都具有特定的码字头以形成多个部分码字对象（PCO）。 每个PCO根据标题内的信息被映射到逻辑数据轨道上。 在每个逻辑数据轨道上，相邻的PCO被合并以形成被调制编码并被映射到同步的CO中的CO。 然后将T同步的CO同时写入数据磁带，其中T是数据磁带上的并发活动磁道的数量。

公开(公告)号：US07679535B2

公开(公告)日：2010-03-16

申请号：US12185095

申请日：2008-08-03

申请人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

发明人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Thomas Mittelholzer ,  Paul J. Seger ,  Keisuke Tanaka

IPC分类号： H03M5/00

CPC分类号： H03M5/145 ,  G11B20/1426 ,  G11B2020/1446 ,  G11B2020/1473 ,  G11B2220/90 ,  G11B2220/956

摘要： An unencoded m-bit data input sequence is divided into a block of n bits and a block of m−n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m−n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.

摘要翻译： 未编码的m位数据输入序列被分成n位块和m-n位块。 n位的块被划分为第一组n + 1个编码比特，其中第一组的P1个子块中的至少一个满足G，M和I约束。 第一组n + 1个编码比特被映射到n + 1编码比特的第二组，其中第二组的P2子块中的至少一个在1 /（1 + D2）预编码之后产生至少Q1个转换。 将第n + 1编码比特的第二组划分为P3编码子块，并且在（m-n）/ s个未编码符号之间交织P3编码子块，以形成第（m + 1）比特的输出序列码字 存储在数据存储介质上。