Power transfer device
    1.
    发明授权
    Power transfer device 有权
    电力传输装置

    公开(公告)号:US09240690B2

    公开(公告)日:2016-01-19

    申请号:US13608426

    申请日:2012-09-10

    摘要: A power transfer device is provided. The power transfer device includes a circuit arrangement including a primary side having a primary coil; a secondary side having a secondary coil inductively coupled to the primary coil and a load transformation unit; wherein the load transformation unit includes an inductor and a capacitor; wherein the secondary coil, the inductor and the capacitor respectively includes a first terminal and a second terminal; wherein the first terminal of the secondary coil is coupled to the first terminal of the capacitor, the second terminal of the capacitor is coupled to the first terminal of the inductor, and the second terminal of the inductor is coupled to the second terminal of the secondary coil.

    摘要翻译: 提供电力传输装置。 电力传送装置包括:电路装置,包括具有初级线圈的初级侧; 次级侧具有感应耦合到初级线圈的次级线圈和负载变换单元; 其中所述负载变换单元包括电感器和电容器; 其中所述次级线圈,所述电感器和所述电容器分别包括第一端子和第二端子; 其中所述次级线圈的第一端子耦合到所述电容器的所述第一端子,所述电容器的第二端子耦合到所述电感器的所述第一端子,并且所述电感器的所述第二端子耦合到所述次级线圈的所述第二端子 线圈

    Power Transfer Device
    2.
    发明申请
    Power Transfer Device 有权
    电力传输装置

    公开(公告)号:US20130062962A1

    公开(公告)日:2013-03-14

    申请号:US13608426

    申请日:2012-09-10

    IPC分类号: H01F38/14 G05F1/10 H02M7/217

    摘要: A power transfer device is provided. The power transfer device includes a circuit arrangement including a primary side having a primary coil; a secondary side having a secondary coil inductively coupled to the primary coil and a load transformation unit; wherein the load transformation unit includes an inductor and a capacitor; wherein the secondary coil, the inductor and the capacitor respectively includes a first terminal and a second terminal; wherein the first terminal of the secondary coil is coupled to the first terminal of the capacitor, the second terminal of the capacitor is coupled to the first terminal of the inductor, and the second terminal of the inductor is coupled to the second terminal of the secondary coil.

    摘要翻译: 提供电力传输装置。 电力传送装置包括:电路装置,包括具有初级线圈的初级侧; 次级侧具有感应耦合到初级线圈的次级线圈和负载变换单元; 其中所述负载变换单元包括电感器和电容器; 其中所述次级线圈,所述电感器和所述电容器分别包括第一端子和第二端子; 其中所述次级线圈的第一端子耦合到所述电容器的所述第一端子,所述电容器的第二端子耦合到所述电感器的所述第一端子,并且所述电感器的所述第二端子耦合到所述次级线圈的所述第二端子 线圈

    3-transistor OTP ROM using CMOS gate oxide antifuse
    3.
    发明授权
    3-transistor OTP ROM using CMOS gate oxide antifuse 失效
    使用CMOS栅极氧化物反熔丝的3晶体管OTP ROM

    公开(公告)号:US06927997B2

    公开(公告)日:2005-08-09

    申请号:US10866251

    申请日:2004-06-14

    IPC分类号: G11C17/00 G11C11/34 G11C17/16

    CPC分类号: G11C17/16

    摘要: The present invention relates to an OTP ROM using a CMOS gate oxide antifuse. According to an embodiment of the present invention, in an OTP ROM cell having a first input terminal, a second input terminal and a third input terminal, wherein the OTP ROM stores data by means of a voltage applied to the first to third input terminals, the OTP ROM cell includes a cell access transistor having a gate and drain forming the second input terminal and a source forming the first input terminal, wherein the cell access transistor is activated by a voltage applied to between the gate and source, a high-voltage blocking transistor having a gate, a drain and a source connected to the drain of the cell access transistor, wherein the high-voltage blocking transistor allows the current to flow from the drain to the source by means of a bias voltage applied to the gate, thus blocking the high voltage applied to the third input terminal from being directly applied to the cell access transistor, and an antifuse transistor having a gate forming the third input terminal, and source and drain both of which are connected to each other and are then connected to the drain of the high-voltage blocking transistor, wherein a high voltage is applied to the third input terminal and if the cell access transistor is activated, gate oxide is broken and shorted.

    摘要翻译: 本发明涉及使用CMOS栅极氧化物反熔丝的OTP ROM。 根据本发明的实施例,在具有第一输入端子,第二输入端子和第三输入端子的OTP ROM单元中,其中OTP ROM通过施加到第一至第三输入端子的电压来存储数据, OTP ROM单元包括具有形成第二输入端的栅极和漏极的单元存取晶体管和形成第一输入端的源,其中,单元存取晶体管由施加到栅极和源极之间的电压而被激活,高电压 阻挡晶体管具有栅极,漏极和源极,连接到电池存取晶体管的漏极,其中高压阻断晶体管允许电流通过施加到栅极的偏置电压从漏极流到源极, 从而阻止施加到第三输入端子的高电压直接施加到电池存取晶体管,以及具有形成第三输入端子的栅极的反熔丝晶体管,源极 nd漏极,它们彼此连接并且然后连接到高压阻断晶体管的漏极,其中高电压被施加到第三输入端子,并且如果电池存取晶体管被激活,则栅极氧化物被断开,并且 短路

    3-Transistor OTP ROM using CMOS gate oxide antifuse
    4.
    发明申请
    3-Transistor OTP ROM using CMOS gate oxide antifuse 失效
    3晶体管OTP ROM采用CMOS栅极氧化物反熔丝

    公开(公告)号:US20050007855A1

    公开(公告)日:2005-01-13

    申请号:US10866251

    申请日:2004-06-14

    IPC分类号: G11C17/00 G11C11/34 G11C17/16

    CPC分类号: G11C17/16

    摘要: The present invention relates to an OTP ROM using a CMOS gate oxide antifuse. According to an embodiment of the present invention, in an OTP ROM cell having a first input terminal, a second input terminal and a third input terminal, wherein the OTP ROM stores data by means of a voltage applied to the first to third input terminals, the OTP ROM cell includes a cell access transistor having a gate and drain forming the second input terminal and a source forming the first input terminal, wherein the cell access transistor is activated by a voltage applied to between the gate and source, a high-voltage blocking transistor having a gate, a drain and a source connected to the drain of the cell access transistor, wherein the high-voltage blocking transistor allows the current to flow from the drain to the source by means of a bias voltage applied to the gate, thus blocking the high voltage applied to the third input terminal from being directly applied to the cell access transistor, and an antifuse transistor having a gate forming the third input terminal, and source and drain both of which are connected to each other and are then connected to the drain of the high-voltage blocking transistor, wherein a high voltage is applied to the third input terminal and if the cell access transistor is activated, gate oxide is broken and shorted.

    摘要翻译: 本发明涉及使用CMOS栅极氧化物反熔丝的OTP ROM。 根据本发明的实施例,在具有第一输入端子,第二输入端子和第三输入端子的OTP ROM单元中,其中OTP ROM通过施加到第一至第三输入端子的电压来存储数据, OTP ROM单元包括具有形成第二输入端的栅极和漏极的单元存取晶体管和形成第一输入端的源,其中单元存取晶体管由施加到栅极和源极之间的电压而被激活,高电压 阻挡晶体管具有栅极,漏极和源极,连接到电池存取晶体管的漏极,其中高压阻断晶体管允许电流通过施加到栅极的偏置电压从漏极流到源极, 从而阻止施加到第三输入端子的高电压直接施加到电池存取晶体管,以及具有形成第三输入端子的栅极的反熔丝晶体管,源极 nd漏极,它们彼此连接并且然后连接到高压阻断晶体管的漏极,其中高电压被施加到第三输入端子,并且如果电池存取晶体管被激活,则栅极氧化物被断开,并且 短路