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    Method and apparatus for protecting, optimizing, and reporting synchronizers
    3.
    发明授权
    Method and apparatus for protecting, optimizing, and reporting synchronizers 有权
    用于保护，优化和报告同步器的方法和装置

    公开(公告)号：US08732639B1

    公开(公告)日：2014-05-20

    申请号：US12384377

    申请日：2009-04-03

    申请人： Ryan Fung ,  Vaughn Betz ,  David Neto

    发明人： Ryan Fung ,  Vaughn Betz ,  David Neto

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5054 ,  G06F2217/84

    摘要： A method for designing a system on a target device using an electronic design automation (EDA) tool including identifying synchronizer chains in a system design using timing relationships. According to one embodiment of the present invention, the method includes conveniently reporting system reliability considering synchronization, and automatically protecting and optimizing synchronizer chains to improve system robustness.

    摘要翻译： 一种使用电子设计自动化（EDA）工具在目标设备上设计系统的方法，包括使用定时关系在系统设计中识别同步器链。 根据本发明的一个实施例，该方法包括方便地报告考虑同步的系统可靠性，并且自动保护和优化同步器链以提高系统的鲁棒性。

    Automatic asynchronous signal pipelining
    4.
    发明授权
    Automatic asynchronous signal pipelining 有权
    自动异步信号流水线

    公开(公告)号：US07676768B1

    公开(公告)日：2010-03-09

    申请号：US11437950

    申请日：2006-05-19

    申请人： Mark Bourgeault ,  Ryan Fung ,  David Lewis

    发明人： Mark Bourgeault ,  Ryan Fung ,  David Lewis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/00323 ,  H03K19/17736

    摘要： An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals. The technique has utility for high-performance FPGAs and structured ASIC families, as well as for low-cost FPGAs and other types of logic devices.

    摘要翻译： 电子设计自动化（EDA）工具改变用户的网表以提供异步信号分配的时序成功。 分配网络在分配缓冲区之前和/或之后添加流水线寄存器时使用。 或者，在异步源和目标寄存器之间插入一条流水线寄存器树。 或者，任何数量的分发网络被缝合在一起，并且可以在每个分发缓冲器之前和/或之后插入流水线阶段。 或者，通过引入偏移时钟信号的延迟分量来利用有益的偏移。 偏斜时钟信号驱动在分配缓冲器之前插入的流水线寄存器，以便提高定时裕度。 可以在EDA工具中使用各种编译技术中的任何一种来解决分配高速，高扇出异步信号的问题。 该技术可用于高性能FPGA和结构化ASIC系列，以及低成本FPGA和其他类型的逻辑器件。

    Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
    5.
    发明授权
    Apparatus for using metastability-hardened storage circuits in logic devices and associated methods 有权
    在逻辑器件和相关方法中使用亚稳态硬化存储电路的装置

    公开(公告)号：US07977975B1

    公开(公告)日：2011-07-12

    申请号：US12563088

    申请日：2009-09-18

    申请人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

    发明人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

    IPC分类号： H03K19/00

    CPC分类号： H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

    摘要： An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

    摘要翻译： 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。

    Method and apparatus for reducing power spikes caused by clock networks
    7.
    发明授权
    Method and apparatus for reducing power spikes caused by clock networks 有权

    公开(公告)号：US08558599B1

    公开(公告)日：2013-10-15

    申请号：US12589031

    申请日：2009-10-16

    申请人： David Lewis ,  Ryan Fung

    发明人： David Lewis ,  Ryan Fung

    IPC分类号： H03K5/00 ,  H03K19/00

    CPC分类号： H03K5/00 ,  G06F1/10 ,  G06F1/26 ,  H03K19/00346

    摘要： A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.

    Automatic asynchronous signal pipelining
    8.
    发明授权
    Automatic asynchronous signal pipelining 有权

    公开(公告)号：US08539414B1

    公开(公告)日：2013-09-17

    申请号：US12651982

    申请日：2010-01-04

    申请人： Mark Bourgeault ,  Ryan Fung ,  David Lewis

    发明人： Mark Bourgeault ,  Ryan Fung ,  David Lewis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/00323 ,  H03K19/17736

    摘要： An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals. The technique has utility for high-performance FPGAs and structured ASIC families, as well as for low-cost FPGAs and other types of logic devices.

    APPARATUS FOR USING METASTABILITY-HARDENED STORAGE CIRCUITS IN LOGIC DEVICES AND ASSOCIATED METHODS
    9.
    发明申请
    APPARATUS FOR USING METASTABILITY-HARDENED STORAGE CIRCUITS IN LOGIC DEVICES AND ASSOCIATED METHODS 有权
    在逻辑设备和相关方法中使用可扩展性硬化存储电路的设备

    公开(公告)号：US20110227625A1

    公开(公告)日：2011-09-22

    申请号：US13149774

    申请日：2011-05-31

    申请人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

    发明人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

    IPC分类号： H03K3/02

    CPC分类号： H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

    摘要： An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

    摘要翻译： 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。