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公开(公告)号：US20090028280A1
公开(公告)日：2009-01-29
申请号：US12280726
申请日：2007-01-09
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , G09G5/008 , G09G2370/12 , H04N21/242 , H04N21/4302
摘要： A clock control circuit 22 in a control circuit 21 provided in a transmitter 25 controls a gate circuit 12 based on an instruction from a microcomputer 32 to stop the output of the clock to a cable 115 for a first predetermined period of time. Then, a read-out circuit in the microcomputer 32 accesses an EDID 31 stored in an information storing circuit of a receiver 43 via the cable 115, and specifies the first predetermined period of time based on the EDID 31. A reconfiguration circuit 42 provided in the receiver 43 counts the clock-holding state, and resets at least one of the receiver 43 and a TV 114 if the clock has been stopped for a second predetermined period of time. This reset operation suppresses the display of noise on the TV 114. Therefore, the occurrence of noise due to mis-latching between the clock and the data can be reduced even after a signal switching that entails a change in the clock frequency.
摘要翻译： 设置在发送器25中的控制电路21中的时钟控制电路22基于来自微型计算机32的指令来控制门电路12，以在第一预定时间段内将时钟的输出停止到电缆115。 然后，微计算机32中的读出电路通过电缆115访问存储在接收机43的信息存储电路中的EDID 31，并基于EDID 31指定第一预定时间段。一种重配置电路42， 接收器43计数时钟保持状态，并且如果时钟已经停止了第二预定时间段，则复位接收器43和TV 114中的至少一个。 该复位操作抑制TV 114上的噪声的显示。因此，即使在需要时钟频率变化的信号切换之后，也可以减少由于时钟和数据之间的误锁而引起的噪声的发生。
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公开(公告)号：US20090052599A1
公开(公告)日：2009-02-26
申请号：US12279765
申请日：2006-11-30
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , G09G5/008 , G09G2320/0238 , H03L7/16 , H03M9/00 , H04N21/4122 , H04N21/43632
摘要： The present invention provides a transmitter capable of reducing the occurrence of noise when switching from the SD signal to the HD signal, for example. A microcomputer (151) controls a 10-times multiplication PLL (13) to increase the amount of jitter of a multiplied clock (CLK1×10) upon signal switching, i.e., when switching the frequency of an input clock (CLK1) from one to another. Alternatively, it controls a phase adjustment section (31) to increase the amount of jitter of a transmit clock (CLK2). Alternatively, it controls a fixed data producing section (61) to set transmit data (DATA2) to predetermined fixed data stored in a fixed data storing section (62).
摘要翻译： 本发明提供了一种例如在从SD信号切换到HD信号时能够减少噪声的发生的发送机。 微控制器（151）控制10倍乘法PLL（13），以便在信号切换时，即当将输入时钟（CLK1）的频率从一个切换到另一个时，增加倍增时钟（CLK1×10）的抖动量。 或者，它控制相位调整部分（31）以增加发送时钟（CLK2）的抖动量。 或者，它控制固定数据产生部分（61）将发送数据（DATA2）设置为存储在固定数据存储部分（62）中的预定固定数据。
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公开(公告)号：US07565473B2
公开(公告)日：2009-07-21
申请号：US11403807
申请日：2006-04-14
IPC分类号： H05K7/10
CPC分类号： G06F13/4081 , Y02D10/14 , Y02D10/151
摘要： In a semiconductor integrated circuit, a detection confirmation circuit sets the logical level of a second signal according to the logical level of a first signal observed after a lapse of a predetermined time since detection of insertion/removal of a cable for peripheral equipment. The semiconductor integrated circuit operates in a standby mode in which only the insertion/removal detection circuit operates if no cable for peripheral equipment is connected, in a repeater mode in which only PHY operates if a cable for peripheral equipment is connected and CPU is in the suspended state, and in a normal mode in which both PHY and LINK operate if a cable for peripheral equipment is connected and a CPU is in the operating state.
摘要翻译： 在半导体集成电路中，检测确认电路根据从检测到用于外围设备的电缆的插入/拔出之后经过预定时间后观察到的第一信号的逻辑电平来设置第二信号的逻辑电平。 半导体集成电路在待机模式下工作，其中仅在没有连接用于外围设备的电缆的情况下仅在连接了用于外围设备的电缆的CPU的中继器模式中才插入/移除检测电路，并且CPU处于 并且在正常模式下，如果连接了用于外围设备的电缆，并且CPU处于工作状态，PHY和LINK两者都将工作。
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公开(公告)号：US20060252184A1
公开(公告)日：2006-11-09
申请号：US11403807
申请日：2006-04-14
IPC分类号： H01L21/82
CPC分类号： G06F13/4081 , Y02D10/14 , Y02D10/151
摘要： In a semiconductor integrated circuit, a detection confirmation circuit sets the logical level of a second signal according to the logical level of a first signal observed after a lapse of a predetermined time since detection of insertion/removal of a cable for peripheral equipment. The semiconductor integrated circuit operates in a standby mode in which only the insertion/removal detection circuit operates if no cable for peripheral equipment is connected, in a repeater mode in which only PHY operates if a cable for peripheral equipment is connected and CPU is in the suspended state, and in a normal mode in which both PHY and LINK operate if a cable for peripheral equipment is connected and a CPU is in the operating state.
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5.发明授权Semiconductor integrated circuit apparatus comprising clock signal line formed in a ring shape 失效半导体集成电路装置，包括形成环状的时钟信号线
公开(公告)号：US5396129A
公开(公告)日：1995-03-07
申请号：US66225
申请日：1993-05-25
申请人： Yoshihiro Tabira
发明人： Yoshihiro Tabira
IPC分类号： H03K5/15 , H03K19/003 , H03K19/096
CPC分类号： H03K19/00323 , H03K5/15066
摘要： In a semiconductor integrated circuit apparatus, a first logic circuit processes a clock signal inputted through an external clock input terminal, and each of a plurality of second logic circuits processes the clock signal outputted from the first logic circuit, and outputs the processed clock signal to a plurality of flip-flops. In the semiconductor integrated circuit apparatus, an inner clock signal line is provided for electrically connecting the plurality of second logic circuits with the plurality of flip-flops, wherein the inner clock signal line is formed in a ring shape in the periphery of the semiconductor integrated circuit apparatus so that the plurality of flip-flops are located within the inner clock signal line, thereby reducing the clock skews therebetween in the semiconductor integrated circuit. Furthermore, an outer clock signal line is provided for electrically connecting the first logic circuit with the plurality of second logic circuits, and then the outer clock signal line is formed in a ring shape, thereby further reducing the clock skews therebetween in the semiconductor integrated circuit.
摘要翻译： 在半导体集成电路装置中，第一逻辑电路处理通过外部时钟输入端子输入的时钟信号，并且多个第二逻辑电路中的每一个处理从第一逻辑电路输出的时钟信号，并将处理的时钟信号输出到 多个触发器。 在半导体集成电路装置中，提供内部时钟信号线，用于将多个第二逻辑电路与多个触发器电连接，其中内部时钟信号线在半导体集成的外围形成为环形 电路装置，使得多个触发器位于内部时钟信号线内，从而减少半导体集成电路中的时钟偏差。 此外，提供外部时钟信号线用于将第一逻辑电路与多个第二逻辑电路电连接，然后外部时钟信号线形成为环形形状，从而进一步减小半导体集成电路中的时钟偏差 。
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公开(公告)号：US20060236009A1
公开(公告)日：2006-10-19
申请号：US11400531
申请日：2006-04-10
申请人： Yoshihiro Tabira
发明人： Yoshihiro Tabira
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F12/1081 , G06F13/385
摘要： A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus.
摘要翻译： 数据发送器包括总线主电路。 总线主电路获得使用CPU总线的权利，并通过CPU接口部分和CPU总线直接执行连接到CPU总线的工作内存的数据传输。
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公开(公告)号：US07380037B2
公开(公告)日：2008-05-27
申请号：US11400531
申请日：2006-04-10
申请人： Yoshihiro Tabira
发明人： Yoshihiro Tabira
CPC分类号： G06F13/28 , G06F12/1081 , G06F13/385
摘要： A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus.
摘要翻译： 数据发送器包括总线主电路。 总线主电路获得使用CPU总线的权利，并通过CPU接口部分和CPU总线直接执行连接到CPU总线的工作内存的数据传输。
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公开(公告)号：US07127530B2
公开(公告)日：2006-10-24
申请号：US10124265
申请日：2002-04-18
申请人： Isamu Ishimura , Yoshihiro Tabira
发明人： Isamu Ishimura , Yoshihiro Tabira
CPC分类号： G06F13/126
摘要： In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.
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公开(公告)号：US06654380B1
公开(公告)日：2003-11-25
申请号：US09497194
申请日：2000-02-03
IPC分类号： H04L2900
摘要： Reception buffer, transmission buffer, transmission-reception buffer, reception filter and transmission filter are provided. The reception filter determines where a received packet should be stored based on the contents of the received packet. Specifically, in executing a READ command, a response packet, which is returned in response to a data transmission packet, is detected by the reception filter. Received packets of the other types are stored on the reception buffer. In executing a WRITE command, a data request packet is transmitted from the transmission buffer. A data reception packet responding to the data request packet is stored by the reception filter on the transmission-reception buffer. Received packets of the other types are stored on the reception buffer. The capacity of the transmission-reception buffer is twice as large as the size of a maximum transferable packet. Thus, overhead can be reduced and yet data can be transferred at higher speeds.
摘要翻译： 提供接收缓冲器，发送缓冲器，发送接收缓冲器，接收滤波器和发送滤波器。 接收过滤器基于接收到的分组的内容来确定应该存储接收分组的位置。 具体地，在执行READ命令时，接收过滤器检测响应于数据传输分组返回的响应分组。 接收到的其他类型的数据包被存储在接收缓冲器中。 在执行WRITE命令时，从发送缓冲器发送数据请求分组。 响应于数据请求分组的数据接收分组由接收滤波器存储在发送接收缓冲器上。 接收到的其他类型的数据包被存储在接收缓冲器中。 发送接收缓冲器的容量是最大可传输分组的大小的两倍。 因此，可以降低开销，并且可以以更高的速度传输数据。
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公开(公告)号：US20070180336A1
公开(公告)日：2007-08-02
申请号：US11640868
申请日：2006-12-19
申请人： Hirotaka Ito , Yoshihiro Tabira
发明人： Hirotaka Ito , Yoshihiro Tabira
IPC分类号： G06F11/00
CPC分类号： H04L12/40071 , H04L12/6418 , H04L69/22
摘要： The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circuits each for controlling a command processing sequence performed with the corresponding device; a multi-control circuit for giving sequence execution permission to one of the plurality of command control circuits; and a packet processing circuit for generating a packet containing information output by the permission-given command control circuit and outputting the packet for transmission, and also outputting a received packet according to the analysis results output by the packet filter.
摘要翻译： 用于通过传输线连接的多个设备中的每一个进行分组单元通信的多发起者控制单元包括：分组过滤器，用于分析接收的分组并输出结果; 多个命令控制电路，用于控制与相应装置执行的命令处理顺序; 用于向所述多个命令控制电路之一提供序列执行许可的多控制电路; 以及分组处理电路，用于生成包含由许可命令控制电路输出的信息的分组并输出用于传输的分组，并且还根据分组过滤器输出的分析结果输出接收的分组。
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