利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

3 条记录 (耗时 0.014 秒)

    Recorded data demodulation circuit
    1.
    发明授权
    Recorded data demodulation circuit 失效
    记录数据解调电路

    公开(公告)号：US5021894A

    公开(公告)日：1991-06-04

    申请号：US459419

    申请日：1990-01-02

    申请人： Ryuichi Naito ,  Keiji Kinpara

    发明人： Ryuichi Naito ,  Keiji Kinpara

    IPC分类号： G11B7/005 ,  G11B7/007 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14

    CPC分类号： G11B20/10037 ,  G11B20/1217 ,  G11B20/1403 ,  G11B7/0052 ,  G11B7/00745

    摘要： A clock of a predetermined frequency is generated on a basis of clock information contained in a read signal. Sample values obtained by sampling the read signal in response to the clock are sequentially converted into digital data, and the thus obtained digital data are held in a first data holding means and then second data holding means in response to the clock for a time corresponding to the clock. The digital data and the output data from the second data holding means are added, and the addition output bits are multiplied by a predetermined constant by inserting a selected number of zero bits as upper significant bits, and shifting the addition output bits by the selected number of zero bits. Data corresponding to the difference between the multiplied output and the output of the first data holding means is obtained, and the thus obtained difference output is demodulated in response to the clock.

    摘要翻译： 基于读取信号中包含的时钟信息产生预定频率的时钟。 通过对读取信号进行采样而获得的采样值被顺序地转换为数字数据，并将这样获得的数字数据保存在第一数据保持装置中，然后将第二数据保持装置响应于时钟响应一段时间 时钟。 将来自第二数据保持装置的数字数据和输出数据相加，并且通过将所选择的零位数作为高有效位插入，并将相加输出位移位所选数字，将相加输出位乘以预定常数 零位。 获得对应于第一数据保持装置的相乘输出和输出之间的差的数据，并且由此获得的差输出响应于时钟被解调。

    Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock
    3.
    发明授权
    Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock 失效
    时钟发生器电路和采样格式系统中的同步信号检测方法以及适合于产生时钟的相位比较器电路

    公开(公告)号：US4872155A

    公开(公告)日：1989-10-03

    申请号：US162625

    申请日：1988-03-01

    申请人： Fumihiko Yokogawa ,  Hiroyuki Hirano ,  Keiji Kinpara

    发明人： Fumihiko Yokogawa ,  Hiroyuki Hirano ,  Keiji Kinpara

    IPC分类号： G11B20/14 ,  G11B20/18 ,  G11B27/19 ,  G11B27/30 ,  G11B27/36 ,  H03L7/087 ,  H03L7/095

    CPC分类号： G11B27/36 ,  G11B20/1403 ,  G11B27/19 ,  G11B27/3027 ,  H03L7/087 ,  H03L7/095 ,  G11B20/1879

    摘要： A recording-reproducing clock generator circuit generates a reproduced clock having a predetermined frequency from a read out signal including such pulses that the interval between two successive pulses thereof at a predetermined length is to be used as a synchronizing signal region. The circuit generates a reference clock of a predetermined frequency, generates a first sync signal detection signal when the distance between two successive pulses in the input signal measured by means of the clock pulses is equal to a predetermined reference value, separates a clock edge pulse from the input signal by using the first sync signal detection signal, and generates the reproduced clock having the predetermined frequency and synchronized with the separated clock edge pulse.

    摘要翻译： 记录再现时钟发生器电路从包括这样的脉冲的读出信号产生具有预定频率的再现时钟，使得其预定长度的两个连续脉冲之间的间隔被用作同步信号区域。 电路产生预定频率的参考时钟，当通过时钟脉冲测量的输入信号中的两个连续脉冲之间的距离等于预定的参考值时，产生第一同步信号检测信号，将时钟脉冲与 通过使用第一同步信号检测信号输入信号，并产生具有预定频率并与分离的时钟边缘脉冲同步的再生时钟。