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    Pulling-in circuit for PLL circuit, pulling-in method for PLL circuit, PLL circuit device and apparatus for reproducing optical disc
    1.
    发明授权
    Pulling-in circuit for PLL circuit, pulling-in method for PLL circuit, PLL circuit device and apparatus for reproducing optical disc 失效
    PLL电路的拉入电路，PLL电路的拉入方法，PLL电路装置以及用于再现光盘的装置

    公开(公告)号：US5619484A

    公开(公告)日：1997-04-08

    申请号：US540982

    申请日：1995-10-11

    申请人： Hiroshi Yokota ,  Ryuichi Naito ,  Hiroyuki Hirano ,  Katsumi Ishii ,  Shinichi Naohara ,  Yoshifumi Tsukada ,  Kanya Matsumoto

    发明人： Hiroshi Yokota ,  Ryuichi Naito ,  Hiroyuki Hirano ,  Katsumi Ishii ,  Shinichi Naohara ,  Yoshifumi Tsukada ,  Kanya Matsumoto

    IPC分类号： G11B7/0037 ,  G11B19/247 ,  G11B19/28 ,  G11B20/12 ,  G11B20/14 ,  H03L7/095 ,  H03L7/10 ,  H03L7/12 ,  G11B7/00

    CPC分类号： H03L7/10 ,  G11B19/247 ,  G11B20/1403 ,  H03L7/095 ,  H03L7/12 ,  G11B20/1258 ,  G11B7/0037

    摘要： A PLL circuit, to which an input signal is inputted, is provided with: a voltage controlled oscillator for outputting an output signal; a control voltage generation circuit for generating a control voltage to lock phases of the input and output signals by a loop, and outputting the generated control voltage to a control input terminal of the voltage controlled oscillator; and a central frequency setting circuit for setting a central frequency, to which a frequency of the output signal is to be pulled-in, to the control voltage generation circuit. A pulling-in circuit for the PLL circuit is provided with: a sweep range setting circuit for setting a sweep range, where the frequency of the output signal is to be pulled-in to the set central frequency, on the basis of the set central frequency; a lock detector for detecting whether or not a pulling-in operation is completed in the PLL circuit, and outputting a lock signal when the pulling-in operation is detected to be completed; and a sweep range control circuit for controlling the control signal generation circuit to generate the control signal to repeatedly sweep the frequency of the output signal through the set sweep range during the pulling-in operation until the lock signal is supplied thereto.

    摘要翻译： 输入输入信号的PLL电路具有：输出输出信号的压控振荡器; 控制电压产生电路，用于产生用于通过一个环路锁定输入和输出信号的相位的控制电压，并将产生的控制电压输出到压控振荡器的控制输入端; 以及用于将输出信号的频率要被拉入的中心频率设定到控制电压产生电路的中心频率设定电路。 用于PLL电路的拉入电路设置有：扫描范围设置电路，用于根据设定的中央点将输出信号的频率拉入设定的中心频率的扫描范围 频率; 锁定检测器，用于检测在PLL电路中是否完成了拉入操作，并且当检测到所述拉入操作完成时输出锁定信号; 以及扫描范围控制电路，用于控制控制信号生成电路，以产生控制信号，以在拉入操作期间通过设定的扫描范围反复扫描输出信号的频率，直到向其提供锁定信号。

    Recorded data demodulation circuit
    2.
    发明授权
    Recorded data demodulation circuit 失效
    记录数据解调电路

    公开(公告)号：US5021894A

    公开(公告)日：1991-06-04

    申请号：US459419

    申请日：1990-01-02

    申请人： Ryuichi Naito ,  Keiji Kinpara

    发明人： Ryuichi Naito ,  Keiji Kinpara

    IPC分类号： G11B7/005 ,  G11B7/007 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14

    CPC分类号： G11B20/10037 ,  G11B20/1217 ,  G11B20/1403 ,  G11B7/0052 ,  G11B7/00745

    摘要： A clock of a predetermined frequency is generated on a basis of clock information contained in a read signal. Sample values obtained by sampling the read signal in response to the clock are sequentially converted into digital data, and the thus obtained digital data are held in a first data holding means and then second data holding means in response to the clock for a time corresponding to the clock. The digital data and the output data from the second data holding means are added, and the addition output bits are multiplied by a predetermined constant by inserting a selected number of zero bits as upper significant bits, and shifting the addition output bits by the selected number of zero bits. Data corresponding to the difference between the multiplied output and the output of the first data holding means is obtained, and the thus obtained difference output is demodulated in response to the clock.

    摘要翻译： 基于读取信号中包含的时钟信息产生预定频率的时钟。 通过对读取信号进行采样而获得的采样值被顺序地转换为数字数据，并将这样获得的数字数据保存在第一数据保持装置中，然后将第二数据保持装置响应于时钟响应一段时间 时钟。 将来自第二数据保持装置的数字数据和输出数据相加，并且通过将所选择的零位数作为高有效位插入，并将相加输出位移位所选数字，将相加输出位乘以预定常数 零位。 获得对应于第一数据保持装置的相乘输出和输出之间的差的数据，并且由此获得的差输出响应于时钟被解调。

    Focus servo device of a system for reading out recorded information
    3.
    发明授权
    Focus servo device of a system for reading out recorded information 失效
    用于读出记录信息的系统的聚焦伺服装置

    公开(公告)号：US4637005A

    公开(公告)日：1987-01-13

    申请号：US516372

    申请日：1983-07-22

    申请人： Ryuichi Naito ,  Minoru Kosaka ,  Katsumi Kawamura

    发明人： Ryuichi Naito ,  Minoru Kosaka ,  Katsumi Kawamura

    IPC分类号： G02B7/28 ,  G05D3/00 ,  G05D3/12 ,  G11B7/08 ,  G11B7/09

    CPC分类号： G11B7/0941 ,  G11B7/0908

    摘要： In a system for optically reading out information recorded on a recording medium, the focus servo device includes an object lens supported by a resilient support member and a focus servo loop. The focus loop includes a driving current generating means for generating a driving current of a cylindrical coil of a focus actuator connected to the object lens in accordance with an output signal of a pickup means which includes the object lens. The improvement is that the dc loop gain of the focus servo loop is substantially raised to infinity, so as to reduce the magnitude of the focus error signal which is required to produce the driving current of the cylindrical lens for moving the object lens against the resilient force of the support member. Further, the focus servo device is characterized by a phase retarding circuit for reducing the amount of the phase rotation at the higher frequency range so as to assure the stability of the operation of the focus servo loop.

    摘要翻译： 在用于光学读取记录在记录介质上的信息的系统中，聚焦伺服装置包括由弹性支撑构件和聚焦伺服环路支撑的物镜。 聚焦环包括驱动电流产生装置，用于根据包括物镜的拾取装置的输出信号产生连接到物镜的聚焦致动器的圆柱形线圈的驱动电流。 改进之处在于，聚焦伺服环路的直流回路增益基本上升至无穷大，以便减小产生用于使物镜抵靠弹性的柱面透镜的驱动电流所需的聚焦误差信号的大小 支撑构件的力。 此外，聚焦伺服装置的特征在于用于减小较高频率范围内的相位旋转量的相位延迟电路，以确保聚焦伺服环路的操作的稳定性。

    Signal waveform equalizing circuitry
    7.
    发明授权
    Signal waveform equalizing circuitry 失效
    信号波形均衡电路

    公开(公告)号：US4636745A

    公开(公告)日：1987-01-13

    申请号：US674666

    申请日：1984-11-26

    申请人： Ryuichi Naito

    发明人： Ryuichi Naito

    IPC分类号： H03H11/04 ,  G11B5/035 ,  G11B20/22 ,  H03F1/32 ,  H03F3/191

    CPC分类号： H03F1/3223 ,  G11B20/22 ,  G11B5/035

    摘要： A signal waveform equalizing circuitry for compensating for the distortion of a signal picked up from a magnetic recording medium by means of a magnetic head, including a first network having the transfer function of (1-BS) and a second network made up of passive elements having the transfer function of a multiplication of the transfer function (1+AS) and the transfer function having the integration function, wherein said first and second networks are serially connected. Thus, the circuitry having an overall transfer function which is a multiplication of transfer functions expressed by (1+AS) and (1-BS) respectively (A, B being a constant, and S being j.omega. while .omega. is angular frequency) and a transfer function having an integration function is realized using relatively simple circuit configuration.

    摘要翻译： 一种信号波形均衡电路，用于通过磁头补偿从磁记录介质拾取的信号的失真，该磁头包括具有（1-BS）的传递函数的第一网络和由无源元件 具有传递函数（1 + AS）和具有积分函数的传递函数的乘法的传递函数，其中所述第一和第二网络串联。 因此，电路具有分别由（1 + AS）和（1-BS）表示的传递函数（A，B为常数，S为ωω，ω为ω频率）的乘积的整体传递函数， 使用相对简单的电路配置实现具有集成功能的传递函数。

    Disc drive servo system
    8.
    发明授权
    Disc drive servo system 失效
    盘式驱动伺服系统

    公开(公告)号：US4486795A

    公开(公告)日：1984-12-04

    申请号：US451830

    申请日：1982-12-21

    申请人： Ryuichi Naito

    发明人： Ryuichi Naito

    IPC分类号： G11B19/28 ,  G11B20/10 ,  G11B21/10

    CPC分类号： G11B19/28 ,  G11B20/10527

    摘要： A disc drive servo system for controlling the drive of a disc carrying a binary digital signal wherein the digital signal includes (i) an information signal portion in which the position of an inversion of the digital signal is determined in accordance with an analog information signal and (ii) synchronizing signal portions which include two successive maximum periods of the inversion. The system comprises a timer means for initialing a timing operation upon receipt of an inversion signal and for producing an output signal when no inversion occurs during a time period which is twice as long as the maximum period of the inversion, thereby reproducing a synchronizing signal and ensuring precise control of the disc drive speed even during periods in which the production of a clock signal is not possible.

    摘要翻译： 一种用于控制承载二进制数字信号的盘的驱动的盘驱动器伺服系统，其中数字信号包括（i）根据模拟信息信号确定数字信号的反相位置的信息信号部分，以及 （ii）同步包括反转的两个连续的最大周期的信号部分。 该系统包括：定时装置，用于在接收到反转信号时初始化定时操作，并且用于当在反转的最大周期的两倍的时间段内不发生反转时产生输出信号，从而再现同步信号， 即使在无法生成时钟信号的时段内，也能确保对光盘驱动器速度的精确控制。

    Read-out information signal processing circuit in an optical recording and reproducing system
    9.
    发明授权
    Read-out information signal processing circuit in an optical recording and reproducing system 失效
    在光学记录和再现系统中的读出信息信号处理电路

    公开(公告)号：US5001698A

    公开(公告)日：1991-03-19

    申请号：US561379

    申请日：1990-08-01

    申请人： Ryuichi Naito

    发明人： Ryuichi Naito

    IPC分类号： G11B20/10 ,  G11B7/00 ,  G11B7/004 ,  G11B7/005 ,  G11B11/10 ,  G11B11/105

    CPC分类号： G11B7/004

    摘要： A read-out information signal processing circuit having a switching device for relaying the read-out information signal read-out from a recording medium in an optical recording and reproducing system. The read-out information signal relayed by the switching device is supplied to an A/D converting circuit through DC interrupt means. The switching device is turned off during the recording period. Thus, the variations of DC level supplied to the A/D converting circuit at the transient time from a recording mode to a reproducing mode can be prevented and the dynamic range of A/D converting circuit can be effectively used.

    摘要翻译： 一种读出信息信号处理电路，具有用于在光学记录和再现系统中中继从记录介质读出的读出信息信号的开关装置。 由开关装置中继的读出信息信号通过直流中断装置提供给A / D转换电路。 开关装置在记录期间被关闭。 因此，可以防止在从记录模式到再现模式的瞬时时间提供给A / D转换电路的DC电平的变化，并且可以有效地使用A / D转换电路的动态范围。

    Phase-locked loop detecting circuit
    10.
    发明授权
    Phase-locked loop detecting circuit 失效
    锁相环检测电路

    公开(公告)号：US4535306A

    公开(公告)日：1985-08-13

    申请号：US517554

    申请日：1983-07-27

    申请人： Tadahiro Yamaguchi ,  Ryuichi Naito

    发明人： Tadahiro Yamaguchi ,  Ryuichi Naito

    IPC分类号： H03M5/14 ,  H03L7/095 ,  H04L7/00 ,  H04L25/49 ,  H03L7/00

    CPC分类号： H03L7/095

    摘要： A circuit for detecting a proper locked state between the output of a phase-locked loop clock generating circuit and a timing component of a received composite signal containing both digital information and the timing component. An internal synchronization pulse signal is produced directly in response to the output of the phase-locked loop, and a frame synchronization sequence detection pulse signal is produced by detecting the occurrence of frame synchronization sequences in the composite signal. The internal synchronization pulse signal and the frame synchronization sequence detection pulse signal are compared to determine whether or not they are in time coincidence. If they are not, corresponding to an improperly locked state, a synchronization hunting controller controls the internal synchronization pulse generator to shift the phase of the internal synchronization pulse signal until time coincidence occurs. The output of the synchronization hunting controller is also used a lock detection signal. A frame synchronization signal is produced by delaying the output of the internal synchronization pulse generator.

    摘要翻译： 一种用于检测锁相环时钟产生电路的输出与包含数字信息和定时分量的接收复合信号的定时分量之间的适当锁定状态的电路。 响应于锁相环的输出直接产生内部同步脉冲信号，并且通过检测复合信号中帧同步序列的出现来产生帧同步序列检测脉冲信号。 比较内部同步脉冲信号和帧同步序列检测脉冲信号，以确定它们是否处于时间一致性。 如果不是，则对应于不正确的锁定状态，同步寻道控制器控制内部同步脉冲发生器来移位内部同步脉冲信号的相位，直到发生时间重合。 同步搜索控制器的输出也用于锁定检测信号。 通过延迟内部同步脉冲发生器的输出来产生帧同步信号。