公开(公告)号：US20080020585A1

公开(公告)日：2008-01-24

申请号：US11727403

申请日：2007-03-26

申请人： Ryukichi Shimizu ,  Akhiro Kikuchi ,  Toshihiko Shindo

发明人： Ryukichi Shimizu ,  Akhiro Kikuchi ,  Toshihiko Shindo

IPC分类号： H01L21/306 ,  C23F1/00

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76811

摘要： To provide a manufacturing method for semiconductor manufacturing device that can suppress the development of striations when forming holes by etching an etch target film composed of an inorganic insulating film, a first sacrifice film stacked on this insulating film and having components different from those of the insulating film, a second sacrifice film formed of an inorganic insulating film, whereon a pattern for forming grooves for wiring embedment on the insulating film is formed. In a substrate including a photoresist film, wherein a pattern for forming holes for embedding the wiring material on the upper layer of the above etch target film, a thickness of the above organic layer is greater than a thickness of an etch target layer composed of the above insulating film, the above first sacrifice film and the above second sacrifice film, a mixed gas containing CF4 gas and CHF3 gas is converted into plasma, and the etch target layer is etched by using the plasma.

摘要翻译： 为了提供半导体制造装置的制造方法，其可以通过蚀刻由无机绝缘膜构成的蚀刻目标膜来形成空穴来抑制条纹的发展，第一牺牲膜层叠在该绝缘膜上并且具有与绝缘体不同的成分 膜，由无机绝缘膜形成的第二牺牲膜，其中形成用于形成用于布线埋入绝缘膜的槽的图案。 在包括光致抗蚀剂膜的基板中，其中用于形成用于将布线材料嵌入上述蚀刻靶膜的上层的孔的图案，上述有机层的厚度大于由所述蚀刻目标层构成的蚀刻目标层的厚度 上述绝缘膜，上述第一牺牲膜和上述第二牺牲膜，含有CF 4气体和CHF 3 N 3气体的混合气体被转换成等离子体，并且蚀刻靶 层通过使用等离子体进行蚀刻。

公开(公告)号：US08263498B2

公开(公告)日：2012-09-11

申请号：US11727403

申请日：2007-03-26

申请人： Ryukichi Shimizu ,  Akihiro Kikuchi ,  Toshihiko Shindo

发明人： Ryukichi Shimizu ,  Akihiro Kikuchi ,  Toshihiko Shindo

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76811

摘要： Disclosed is a semiconductor device fabricating method. A substrate is provided thereon with: an inorganic insulating film; a first inorganic sacrifice film stacked on the inorganic insulating film and having components different from those of the inorganic insulating film; a second sacrifice film formed of an inorganic insulative film stacked on the first sacrifice film, wherein a pattern for forming grooves for wiring embedment is formed in the second sacrifice film; and an organic layer including a photoresist film, wherein a pattern for forming holes for wiring embedment is formed in the organic film. According to the present invention, the thickness of the organic layer is set to be greater than the sum of the thicknesses of etch target films, i.e., the insulating film, the first sacrifice film and the second sacrifice film; the etch target films are etched in a selectivity-less manner by using plasma generated from a mixed gas of CF4 gas and CHF3 gas.

摘要翻译： 公开了一种半导体器件制造方法。 在其上设置有：无机绝缘膜; 第一无机牺牲膜堆叠在无机绝缘膜上并且具有与无机绝缘膜不同的成分; 由第一牺牲膜上的无机绝缘膜形成的第二牺牲膜，其中在所述第二牺牲膜中形成用于形成用于布线嵌入的槽的图案; 以及包括光致抗蚀剂膜的有机层，其中在有机膜中形成用于形成用于布线嵌入的孔的图案。 根据本发明，有机层的厚度设定为大于蚀刻目标膜，即绝缘膜，第一牺牲膜和第二牺牲膜的厚度之和; 通过使用由CF 4气体和CHF 3气体的混合气体产生的等离子体，以无选择性的方式蚀刻蚀刻靶膜。

公开(公告)号：US08532796B2

公开(公告)日：2013-09-10

申请号：US13077705

申请日：2011-03-31

申请人： Daniel J Prager ,  Merritt Funk ,  Peter Biolsi ,  Ryukichi Shimizu

发明人： Daniel J Prager ,  Merritt Funk ,  Peter Biolsi ,  Ryukichi Shimizu

IPC分类号： H01L21/66 ,  G06F19/00

CPC分类号： H01L22/20 ,  H01J37/32082 ,  H01J37/3266 ,  H01L21/31116 ,  H01L21/823871 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

摘要翻译： 本发明提供了一种用于在图案化晶片上实时使用双模式接触蚀刻（DPCE）处理序列和相关联的接触蚀刻多输入/多输出（CE- MIMO）模型。 DPCE处理序列可以包括一个或多个接触蚀刻程序，一个或多个测量程序，一个或多个接触蚀刻建模程序以及一个或多个接触蚀刻验证程序。 CE-MIMO模型使用多层和/或多个接触蚀刻程序之间的动态交互行为建模。 多层和/或多层接触蚀刻程序可以与在双重图案化（DP）程序期间可以创建的线，沟槽，通孔，间隔物，接触和门结构的创建相关联。

公开(公告)号：US20120253497A1

公开(公告)日：2012-10-04

申请号：US13077705

申请日：2011-03-31

申请人： Daniel J. Prager ,  Merritt Funk ,  Peter Biolsi ,  Ryukichi Shimizu

发明人： Daniel J. Prager ,  Merritt Funk ,  Peter Biolsi ,  Ryukichi Shimizu

IPC分类号： H01L21/66 ,  G06F19/00

CPC分类号： H01L22/20 ,  H01J37/32082 ,  H01J37/3266 ,  H01L21/31116 ,  H01L21/823871 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

摘要翻译： 本发明提供了一种用于在图案化晶片上实时使用双模式接触蚀刻（DPCE）处理序列和相关联的接触蚀刻多输入/多输出（CE- MIMO）模型。 DPCE处理序列可以包括一个或多个接触蚀刻程序，一个或多个测量程序，一个或多个接触蚀刻建模程序以及一个或多个接触蚀刻验证程序。 CE-MIMO模型使用多层和/或多个接触蚀刻程序之间的动态交互行为建模。 多层和/或多层接触蚀刻程序可以与在双重图案化（DP）程序期间可以创建的线，沟槽，通孔，间隔物，接触和门结构的创建相关联。