公开(公告)号：US20150357349A1

公开(公告)日：2015-12-10

申请号：US14828384

申请日：2015-08-17

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Je Hun LEE ,  Yang Ho BAE ,  Beom-Seok CHO ,  Chang Oh JEONG

IPC: H01L27/12

CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

Abstract translation: 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

公开(公告)号：US20130056740A1

公开(公告)日：2013-03-07

申请号：US13669278

申请日：2012-11-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Je Hun LEE ,  Yang Ho BAE ,  Beom-Seok CHO ,  Chang Oh JEONG

IPC: H01L33/08

CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

公开(公告)号：US20140167054A1

公开(公告)日：2014-06-19

申请号：US14165399

申请日：2014-01-27

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Je Hun LEE ,  Yang Ho BAE ,  Beom-Seok CHO ,  Chang Oh JEONG

IPC: H01L27/12

CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

Abstract translation: 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。