公开(公告)号：US20140361304A1

公开(公告)日：2014-12-11

申请号：US14209066

申请日：2014-03-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Su CHO ,  Hyeong Tag JEON ,  Jae Sang LEE

IPC: H01L29/10 ,  H01L29/786

CPC classification number: H01L29/1033 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor array panel includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and overlapping the gate electrode; a plurality of nano particles disposed on or in the semiconductor layer; a source electrode disposed on the substrate; and a drain electrode disposed on the substrate, where the source electrode and the drain electrode are spaced apart from each other, and the semiconductor layer is disposed between the source electrode and the drain electrode, in which a diameter of each of the nano particles is in a range of about 2 nm to about 5 nm, or a ratio of a plane area of the nano particles per unit area of the semiconductor layer is in a range of about 5% to about 80%.

Abstract translation: 薄膜晶体管阵列面板包括：基板; 设置在所述基板上的栅电极; 半导体层，设置在所述基板上并与所述栅电极重叠; 设置在半导体层上或其中的多个纳米颗粒; 设置在所述基板上的源电极; 以及设置在所述基板上的漏电极，所述源电极和所述漏电极彼此间隔开，并且所述半导体层设置在所述源电极和所述漏电极之间，其中，所述半导体层的每一个所述纳米粒子的直径为 在约2nm至约5nm的范围内，或者半导体层的每单位面积的纳米颗粒的平面面积的比率在约5％至约80％的范围内。