公开(公告)号：US20240071907A1

公开(公告)日：2024-02-29

申请号：US18197768

申请日：2023-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah Reum LEE ,  Woo Sung YANG ,  Ji Mo GU ,  Jao Ho KIM ,  Suk Kang SUNG

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/528 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device includes first and second substrates connected to each other. The second substrate includes a plate layer having first and second faces. Gate electrode layers are disposed on the first face of the plate layer. Channel structures extend through the gate electrode layers. Word-line cutting structures extend through the gate electrode layers and are spaced apart from each other. Via structures are disposed on the second face of the plate layer. Via connecting structures are disposed on the top face of the via structures. A width of the bottom face of each of the via structures is greater than a width of the top face of each of the via structures. A width of the bottom face of each of the via connecting structures is less than a width of the top face of each of the via connecting structures.