公开(公告)号：US20250080119A1

公开(公告)日：2025-03-06

申请号：US18818024

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-Sun Kong ,  Bomin Joo

IPC: H03K23/56 ,  H03K23/44 ,  H03M1/48

Abstract: Disclosed are a bidirectional counter and a method of generating output data. The bidirectional counter may include at least one first flip-flop configured to generate, based on at least one first local clock, at least one first bit including a least significant bit (LSB) of the output data and a second bit that is an upper bit of the at least one first bit, and a local clock generation circuit configured to generate, in response to an up signal that is activated, the at least one first local clock based on the input clock and the at least one first bit, and to generate, in response to the up signal that is deactivated, the at least one first local clock based on the input clock and at least one inverted first bit.

公开(公告)号：US20250070765A1

公开(公告)日：2025-02-27

申请号：US18813909

申请日：2024-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-Sun Kong ,  Bomin Joo

IPC: H03K3/3562 ,  H03K3/012

Abstract: A flip-flop is provided. The flip-flop includes: a master latch; and a slave latch. The master latch includes: a first circuit configured to, based on a clock signal, a data input signal, and a first data signal, generate a second data signal complementary to the data input signal; a second circuit configured to, based on the clock signal, an inverted data input signal, and the second data signal, generate the first data signal complementary to the inverted data input signal; and a third circuit configured to generate a latch signal based on the clock signal, an input of the slave latch, and the second data signal. The slave latch is configured to latch the input of the slave latch based on the clock signal and the latch signal.

公开(公告)号：US20250070764A1

公开(公告)日：2025-02-27

申请号：US18812235

申请日：2024-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-sun Kong ,  Bomin Joo

IPC: H03K3/356 ,  G11C7/06

Abstract: A sense amplifier flip-flop includes a first stage configured to generate, in response to a rising edge of a clock signal, a first latch signal and a second latch signal by pulling down a first pull-down node or a second pull-down node according to a data input and an inverted data input, wherein the first stage includes a bridge circuit configured to electrically connect the first pull-down node and the second pull-down node to each other in response to an activated bridge signal, and a control circuit configured to activate the bridge signal when the data input transitions while the clock signal is logic high.

公开(公告)号：US20250070763A1

公开(公告)日：2025-02-27

申请号：US18812395

申请日：2024-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-Sun Kong ,  Bomin Joo

IPC: H03K3/037

Abstract: A flip-flop configured to generate an output toggling according to an input clock includes an inverter configured to generate the output by inverting a first data signal, a first circuit configured to generate a second data signal based on an input clock and a latch signal, a second circuit configured to generate the latch signal based on the input clock and the second data signal, and a third circuit configured to generate the first data signal using the input clock, the second data signal, and the latch signal, wherein the third circuit is further configured to pull down the first data signal, independently of the second data signal, using the input clock and the latch signal.