公开(公告)号：US11057039B1

公开(公告)日：2021-07-06

申请号：US16949325

申请日：2020-10-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Marcel A. Kossel ,  Vishal Khatri ,  Pier Andrea Francese ,  Matthias Braendli

IPC分类号： H03K21/40 ,  H03K21/02 ,  H03K21/10 ,  H04B1/40 ,  H03K23/44 ,  H03K3/037 ,  H03K5/156 ,  H04L27/36

摘要： The present disclosure relates to a method for quadrature error correction using a frequency divider circuit. The method comprises delaying input of data to master input terminals and/or slave input terminals of the frequency divider circuit for correcting a quadrature error between the in-phase and quadrature-phase output signals.

公开(公告)号：US09647669B1

公开(公告)日：2017-05-09

申请号：US15212411

申请日：2016-07-18

申请人： Texas Instruments Incorporated

发明人： Sudipto Chakraborty

IPC分类号： H03K23/54 ,  H03K23/44

CPC分类号： H03K23/44

摘要： Disclosed examples include frequency divider circuits, comprising an even number 4 or more differential delay circuits coupled in a cascade ring configuration of a configurable length N, with N−K of the N delay circuits providing an inverted polarity output signal to a succeeding delay circuit in the cascade ring configuration to control an amount of overlap between phase shifted clock signals from the delay circuits.

公开(公告)号：US20160315623A1

公开(公告)日：2016-10-27

申请号：US15104243

申请日：2015-11-12

申请人： MEDIATEK SINGAPORE PTE. LTD.

发明人： Christophe C. BEGHEIN ,  Jonathan Richard STRANGE

IPC分类号： H03K23/44 ,  H03D7/14

CPC分类号： H03D7/1458 ,  H03K3/0231 ,  H03K23/44 ,  H03K23/50

摘要： A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the transconductance component of the in-phase mixer circuit. In some examples, at least one switching device within an input switching stage of the regenerative frequency divider forming part of the phase-shifted mixer circuit is of a smaller scale than a respective corresponding switching device within the input switching stage forming part of the in-phase mixer circuit. In some further examples, all switching devices within the phase-shifted mixer circuit are of a small scale than respective corresponding switching devices within the in-phase mixer circuit.

摘要翻译： 一种再生分频器，包括同相混频电路和相移混频电路。 同相混合电路的至少一个开关器件的尺寸小于同相混频器电路的跨导元件的相应开关器件。 在一些示例中，形成相移混频器电路的一部分的再生分频器的输入开关级中的至少一个开关器件的尺寸小于在输入开关级内的相应的开关器件的尺寸， 相混频器电路。 在一些另外的示例中，相移混频器电路内的所有开关器件都具有小于同相混频器电路内的相应开关器件的小尺寸。

公开(公告)号：US20050146362A1

公开(公告)日：2005-07-07

申请号：US11070730

申请日：2005-03-02

申请人： John Austin ,  Ram Kelkar ,  Pradeep Thiagarajan

发明人： John Austin ,  Ram Kelkar ,  Pradeep Thiagarajan

IPC分类号： H03K23/64 ,  H03K5/156 ,  H03K21/00 ,  H03K21/10 ,  H03K21/38 ,  H03K23/44 ,  H03K23/66

CPC分类号： H03K23/667 ,  H03K5/04 ,  H03K5/05 ,  H03K5/1565 ,  H03K21/10 ,  H03K21/38 ,  H03K23/44 ,  H03K23/52

摘要： A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.

公开(公告)号：US6097783A

公开(公告)日：2000-08-01

申请号：US221669

申请日：1998-12-23

申请人： Trevor Monk

发明人： Trevor Monk

IPC分类号： H03K23/44 ,  H03K23/54 ,  H03K23/66 ,  H03L7/183 ,  H03K21/00

CPC分类号： H03K23/66 ,  H03K23/44 ,  H03K23/54 ,  H03K23/667 ,  H03L7/183

摘要： A dividing circuit comprises, connected in a ring, a plurality M of transistor stages, where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage has an input node connected to the output node of a preceding transistor stage in the ring, an enable node connected to the clock nodes of the transistor stages, and an output node connected to the input node of a subsequent transistor stage in the ring. Each transistor stage comprises a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node, and a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, wherein control nodes of a first transistor of each said transistor pair are connected together to provide the input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide the clock node for the stage, whereby when an input clock signal is applied to the clock nodes of the transistor stages, an output signal is generated at the output node of the tri-state inverter in which each cycle represents M cycles of the input clock signal.

摘要翻译： 分频电路包括以环形连接多个M个晶体管级，其中M为偶数整数。 每个晶体管级包括输入节点，时钟节点和输出节点。 三态逆变器级具有连接到环中先前晶体管级的输出节点的输入节点，连接到晶体管级的时钟节点的使能节点和连接到后续晶体管的输入节点的输出节点 在戒指阶段。 每个晶体管级包括串联连接在第一电压电平和输出节点之间的第一导电类型的第一对晶体管，以及串联连接在第二电压电平和所述输出节点之间的第二导电类型的第二对晶体管 其中，每个所述晶体管对的第一晶体管的控制节点连接在一起以提供所述级的输入节点，并且每个所述晶体管对的第二晶体管的控制节点连接在一起以为所述级提供所述时钟节点，由此 当输入时钟信号施加到晶体管级的时钟节点时，在三态反相器的输出节点处产生输出信号，其中每个周期表示输入时钟信号的M个周期。

公开(公告)号：US5572561A

公开(公告)日：1996-11-05

申请号：US466728

申请日：1995-06-06

申请人： Kunihiro Usami ,  Miki Kubota

发明人： Kunihiro Usami ,  Miki Kubota

IPC分类号： H03K23/00 ,  H03B19/00 ,  H03F3/30 ,  H03K3/356 ,  H03K19/0952 ,  H03K23/44 ,  H03K23/54 ,  H03K21/00

CPC分类号： H03K23/44 ,  H03K3/356017

摘要： A frequency dividing circuit includes a first inverter circuit supplied with a first frequency-divided signal, a second inverter circuit supplied with a second frequency-divided signal which has a complementary relationship to the first frequency-divided signal, and a first pair of push-pull circuits. There are also provided a first switch circuit performing a first switching operation in response to a first input signal and selectively supplying output signals of the first and second inverter circuits to the first pair of push-pull circuits so that one of the first pair of push-pull circuits performs a pull-up operation when the other one thereof performs a pull-down operation. Further, there are provided a second pair of push-pull circuits, and a second switch circuit performing a second switching operation in response to a second input signal which has a complementary relationship to the first input signal and selectively supplying output signals of the first pair of push-pull circuits to the second pair of push-pull circuits so that one of the second pair of push-pull circuits performs a pull-up operation when the other one thereof performs a pull-down operation. The first and second frequency-divided signals are output from the second pair of push-pull circuits.

摘要翻译： 分频电路包括被提供有第一分频信号的第一反相器电路，提供有与第一分频信号互补的第二分频信号的第二反相器电路，以及第一对推压信号， 拉电路。 还提供了第一开关电路，其响应于第一输入信号执行第一开关操作，并且选择性地将第一和第二反相器电路的输出信号提供给第一对推挽电路，使得第一对推压 当其中一个执行下拉操作时， - 电路执行上拉操作。 此外，提供了第二对推挽电路和第二开关电路，响应于与第一输入信号具有互补关系的第二输入信号执行第二开关操作，并且选择性地提供第一对的输出信号 的推挽电路到第二对推挽电路，使得第二对推挽电路中的一个在其另一个推挽电路执行下拉操作时执行上拉操作。 第一和第二分频信号从第二对推挽电路输出。

公开(公告)号：US5012497A

公开(公告)日：1991-04-30

申请号：US470273

申请日：1990-01-25

申请人： Swye N. Lee

发明人： Swye N. Lee

IPC分类号： H03K23/44

CPC分类号： H03K23/44

摘要： A frequency divider receives a first frequency signal and at least one clock signal of a sub-multiple of the first frequency. The first frequency signal charges a storage terminal once each first frequency cycle and the sub-multiple frequency signal discharges the storage temrinal once each sub-multiple frequency cycle. The discharged storage terminal sets the frequency divider output which is reset by the first frequency signal when the storage terminal is discharged. The sub-multiple frequency clock signal is employed to control the storage terminal instead of a feedback path from the output to increase the operating frequency of the divider.

摘要翻译： 分频器接收第一频率信号和至少一个第一频率的子倍数的时钟信号。 第一个频率信号对每个第一频率周期一次的存储终端进行充电，并且每个子 - 多个频率周期的次多频率信号放电存储温度。 放电存储终端设置当存储终端被放电时由第一频率信号复位的分频器输出。 采用副多频时钟信号来控制存储终端而不是来自输出端的反馈路径以增加分频器的工作频率。

公开(公告)号：US4646331A

公开(公告)日：1987-02-24

申请号：US718171

申请日：1985-04-01

申请人： Glenn L. Ely

发明人： Glenn L. Ely

IPC分类号： H03K23/44 ,  H03K23/48 ,  H03K21/00

CPC分类号： H03K23/483 ,  H03K23/44

摘要： An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latch stage comprises a first transmission gate and two inverters configured as a latch circuit, and a second transmission gate for coupling the latch circuit to a previous stage. Even-number divider circuits may be implemented using only pairs of switched-latch stages without the bypass circuit.

摘要翻译： 一种电子分频器电路，特别适用于实现奇数计数器，其包括多个开关锁存级，并且在奇数计数器的情况下还包括旁路电路级。 每个切换锁存级包括第一传输门和配置为锁存电路的两个反相器，以及用于将锁存电路耦合到先前级的第二传输门。 偶数分频器电路可以仅使用没有旁路电路的开关锁存器对来实现。

公开(公告)号：US4535465A

公开(公告)日：1985-08-13

申请号：US334486

申请日：1981-12-24

申请人： Jerald G. Leach

发明人： Jerald G. Leach

IPC分类号： G09G3/04 ,  H03K3/02 ,  H03K3/03 ,  H03K5/15 ,  H03K17/687 ,  H03K19/017 ,  H03K19/096 ,  H03K23/44 ,  H03K23/22

CPC分类号： H03K23/44 ,  H03K19/01735 ,  H03K19/096 ,  H03K3/0315 ,  H03K5/1504

摘要： A digital clock generator circuit including a series of inverters connected in cascade with the output of the final stage connected to the input of the first stage in a ring counter fashion. Each inverter includes a first circuit to precharge a node, a second circuit to discharge a node upon occurrence of a selected input signal and a third circuit connected to isolate the node from the circuitry output during the precharge interval. The output of the counter is the output of the final stage. The inverter circuits allow for a low power digital counter by allowing a P-MOS or N-MOS fabrication of devices that do not require continuous power.

摘要翻译： 一种数字时钟发生器电路，包括与环形计数器方式连接到第一级输入端的最终级的输出级联的一系列反相器。 每个逆变器包括用于对节点进行预充电的第一电路，在出现所选择的输入信号时对节点进行放电的第二电路和连接以在预充电间隔期间使节点与电路输出隔离的第三电路。 计数器的输出是最后一级的输出。 通过允许不需要连续功率的器件的P-MOS或N-MOS制造，逆变器电路允许低功率数字计数器。

公开(公告)号：US3940596A

公开(公告)日：1976-02-24

申请号：US571144

申请日：1975-04-24

申请人： Richard Charles Paddock

发明人： Richard Charles Paddock

IPC分类号： H03K23/44 ,  H03K23/02

CPC分类号： H03K23/44

摘要： Dynamic logic counting circuits are disclosed using recirculating latched memory stages having parallel shift circuits operating in synchronism with the latch circuits to control stepping of the counts. An alternate embodiment employs steering circuit controlled subcounters, each subcounter having a parallel shift circuit operating in synchronism with its respective subcounter to step the next succeeding subcounter when its respective subcounter reaches a predetermined count such as 9 for a binary coded decimal counter or 15 for a binary counter.

摘要翻译： 使用具有与锁存电路同步操作的并行移位电路的再循环锁存存储器级来公开动态逻辑计数电路，以控制计数的步进。 替代实施例采用转向电路控制的子计数器，每个子计数器具有与其各自的子计数器同步操作的并行移位电路，以在其相应的子计数器达到预定的计数时进行下一个后续的子计数器，例如对于二进制编码的十进制计数器为9，或者为 二进制计数器。