公开(公告)号：US12100463B2

公开(公告)日：2024-09-24

申请号：US17954663

申请日：2022-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongkil Jung ,  Sangwan Nam ,  Keeho Jung

IPC: G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C29/20 ,  G11C16/04

CPC classification number: G11C29/12015 ,  G11C29/025 ,  G11C29/14 ,  G11C29/20 ,  G11C16/0483

Abstract: Provided are a memory device detecting a defect and an operating method thereof. The memory device includes a memory cell area including a memory cell array that stores data, and a peripheral circuit area including a control logic configured to control operations of the memory cell array, wherein the peripheral circuit area further includes a defect detection circuit, the defect detection circuit being configured to generate a count result value by selecting a first input signal from a plurality of input signals and counting at least one time interval of the first input signal based on a clock signal, and to detect a defect of the first input signal by comparing an expected value with the count result value, and the at least one time interval is a length of time in which logic low or logic high is maintained.

公开(公告)号：US11315651B1

公开(公告)日：2022-04-26

申请号：US17355825

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongkil Jung ,  Dongjin Shin ,  Manjae Yang ,  Byungsun Lee ,  Dongsu Jang

IPC: G11C27/00 ,  G11C5/14 ,  G11C7/10

Abstract: A non-volatile memory device includes a first and a second memory regions including first and second memory cells and first and second analog circuits, respectively; a control logic circuit determining on/off states of the analog circuits, and converting an external power supply voltage into an internal operating voltage for operation of each of the memory cells; and input/output circuit selecting an input/output memory region for performing input/output of data using the internal operating voltage, wherein input/output of data for the first and second memory cells are sequentially performed, and at least one of the each of the first and second analog circuits are turned on together while the input/output of data for the first memory cells is performed.