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公开(公告)号：US11515859B2
公开(公告)日：2022-11-29
申请号：US17372744
申请日：2021-07-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gun-Il Kang , June-Hee Lee , Byung-Wook Cho
Abstract: An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.
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公开(公告)号：US10943524B2
公开(公告)日：2021-03-09
申请号：US16427856
申请日：2019-05-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Chul Choi , Sung-Ho Kang , June-Hee Lee , Han-Kyul Lim , Byung-Wook Cho
Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N−1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N−1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.
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公开(公告)号：US11095271B2
公开(公告)日：2021-08-17
申请号：US16224850
申请日：2018-12-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gun-Il Kang , June-Hee Lee , Byung-Wook Cho
Abstract: An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.
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